ML7204-003 datasheet(60/214 Pages) LAPIS

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FEDL7204-003-02

ML7204-003

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 Receive

 2-channel receive request notification register (RXREQ_DC)

In this operation state, the MCU side is notified that two receive data write requests will be issued in one frame

by setting the 2-channel receive request notification register (RXREQ_DC) to “1”.

 Data write channel sequence

Since data can be written to the channels in any sequence, write receive data in either sequence of CH1

 CH2

or CH2

 CH1 in one frame.

(Note)

Do not write receive data of the same channel in one frame in such a manner as CH1

 CH1 and CH2  CH2.

If receive data of the same channel is written in one frame, the receive data that is written by the first receive

request is decoded; however, the receive data that is written in the second receive request is discarded and an

interrupt is generated by setting a receive side invalid write error flag (RXBW_ERR) to “1”.

 Write procedure

This section describes the operation performed when receive data is written in the sequence of CH1

 CH2.

Write CH1 receive data (80 bytes) according to the first receive data write request (FR1 = 1&RXREQ_First =

1).

Before starting write operation of CH1 receive data, notify the LSI that CH1 receive data will be written by

setting the receive data write channel notification register (RXFLAG_[CH2:CH1]) to [0:1].

After termination of CH1 receive data write processing, the second receive data write request (FR1 = 1 &

RXREQ_First = 0) is issued.

Write CH2 receive data (80 bytes) according to the second write request. In this case also, notify the LSI that

CH2 receive data will be written by setting the receive data write channel notification register

(RXFLAG_[CH2:CH1]) to [1:0], before starting CH2 receive data write processing. When a receive data

write request is issued, an interrupt is generated by setting FR1 to “1” regardless of the first or second request.

(Note)

The setting of RXFLAG_[CH2:CH1] = [1:1] or [0:0] is inhibited at notification of a receive data channel.

If RXFLAG_[CH2:CH1] = [1:1] or [0:0] is set, the receive data is discarded and an interrupt is generated by

setting the receive side invalid write error flag (RXBW_ERR) to “1”.

 Valid write period WE_DCn (CH1 & CH2)

WE_DC1 (CH1 & CH2)

There is no time restriction on the initial valid write period after activation of Speech CODEC (CH1 & CH2).

DEC_OUTON can be set to “1” after a lapse of the tWAIT time following completion of receive data write

processing for CH1 and CH2. Decoding output starts tDECON after DEC_OUTON is set to “1”. (*)

(tWAIT=1ms, tDECON = 0 ms[initial value] ... Can be set within the range from 0.125 to 32 ms in the internal

data memory.)

WE_DC2 (CH1 & CH2)

The second valid write period is 4 ms.

WE_DCn (CH1 & CH2) n = 3, 4, 5, ...

The third valid write period is 9 ms.

(Note) (*)

It is prohibited to change the mode to a single-channel operation mode (SC_EN = 1, DC_EN = 0) before the

decoding output starting offset time elapses after DEC_OUTON is set to “1”.

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