ML7204-003 datasheet(83/214 Pages) LAPIS

83 / 214 page

FEDL7204-003-02

ML7204-003

83/214

(4) CR3

R/W

CR3

TGEN1

_RXAB

TGEN1

_TX

TGEN1

_CNT5

TGEN1

_CNT4

TGEN1

_CNT3

TGEN1

_CNT2

TGEN1

_CNT1

TGEN1

_CNT0

Change enable

mode

I/E

Initial value

R/W

B7: TGEN1 Output control register on the RXAB side

0: Stops output

1: Outputs tone to the RXGENA/RXGENB side

(Note)

Connection/non-connection control is enabled for output paths to RXGENA and RXGENB using the

RXGENA_EN connection path control register (RXGENA_EN) and the RXGENB_EN connection path

control register (RXGENB_EN). Non-connection is set as the initial value.

B6: TGEN1 Output control register on the TX side

0: Stops output

1: Outputs tone to the TXGEN side

See the various generator paths in the block diagram that is shown earlier in this document for RXGENA,

RXGENB, and TXGEN.

B5: Addition and multiplication control register for TONE C/D

0: Addition (Adds output of TONE C and TONE D)

1: Multiplication (Multiplies output of TONE C and TONE D)

B4: Output control register of TONE C/D

0: Single output

Stops by outputting the signal for the time period created by adding TIM_M0 and TIM_M1.

After stopping, this register is automatically cleared within the LSI.

1: Continuous output

Outputs repeatedly the signal that is controlled by the time created by adding TIM_M0 and TIM_M1.

Set 00h to this register when stopping signal output.

(Note)

Do not set any value other than 00h since only 00h is permitted as the value that is written to this register

from continuous output.

At single output, make the next setting after checking that this register is set to 00h.

When outputting signals again after termination of continuous output, wait for a period of “FADE OUT

time + 250

s” or more before starting output.

B3-B2: Output control registers of TONE C

00: Tone is not output.

01: Stops output to the M0 section and outputs tone to the M1 section.

10: Outputs tone to the M0 section and stops output to the M1 section.

11: Outputs tone to the M0 and M1 sections.

B1-B0: Output control registers of TONE D

00: Tone is not output.

01: Stops output to the M0 section and outputs tone to the M1 section.

10: Outputs tone to the M0 section and stops output to the M1 section.

11: Outputs tone to the M0 and M1 sections.

ML7204-003 bảng dữ liệu(PDF) 83 Page - LAPIS Semiconductor Co., Ltd.

ML7204-003 bảng dữ liệu(HTML) 83 Page - LAPIS Semiconductor Co., Ltd.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL