MP7680

10

Rev. 3.10

Transferring

Data to the DAC Latches

Once one or all of the input latches have been loaded, the

condition XFER = WR2= low transfers the content of ALL

the input latches in the DAC latches. The output of the

DAC latches (DA11-DA0) changes and the DAC current

Examples of DACs updating sequences:

1) Simultaneous updates of any number of DACs. The

system uses from one (two) to four (eight) cycles to

write from a 12 (8) bit bus into B1/B2 latches. One

transfer cycle updates the output of all DACs

2) Individual DAC update. The condition WR2 = XFER =

low makes the DAC latches transparent. A writing to

3) Automatic transfer to DAC latches. An 8-bit bus can

update any DAC with two cycles by connecting WR1 =

WR2 and B1/B2= XFER. This is the correct individual

4) Transfer by a second device. A processor may load the

input latches while the final XFER pulse is left to an-

other device.

DATA

CS

WR1

Figure 7. Simultaneous

Updates

of DACs

XFER=WR2

= 0

= 1

= 2

= 3

Valid

Valid

Valid

Valid

CS

DATA

WR1

WR2 = XFER

= 1

= 3

Figure 8. Individual

DAC Update

Valid

Valid

CS

WR1 and WR2

Figure 9. Automatic

Transfer to DAC Latches

= 1

= 2

B1/B2 and XFER