MP7680

8

Rev. 3.10

MUX

0

1

DAC

B1

Latch

B2

Latch

D

E

Q

D

E

Q

D

E

Q

12

4

8

8

4

12

4

8

8

4

DAC

B1

Latch

B2

Latch

D

E

Q

D

E

Q

D

E

Q

12

4

8

8

4

DAC

B1

Latch

B2

Latch

D

E

Q

D

E

Q

D

E

Q

12

4

8

8

4

DAC

B1

Latch

B2

Latch

D

E

Q

D

E

Q

D

E

Q

Latch

Address

Decoder

DA11 - DA0

LA11 - LA0

DAC LA TCHES

INPUT LA TCHES

DB11-DB4

(MSB)

DB3-DB0

(LSB)

B1/B2

A1 (MSB)

A0 (LSB)

CS

WR1

WR2

XFER

DB11-

DB8

Enable A

Enable B

Enable C

Enable D

DB11 - DB0

DC11 - DC0

DD11 - DD0

Transfer

Disable-B1

Figure 3. Latches

Control

Logic

THEOR Y OF OPERA TION

Digital Interface

Figure 3.

shows the internal control logic. The logic that

controls the writing of the input latches and the one that

controls the DAC latches are completely separated. It is

easy to understand how the MP7680/80A works by

understanding each basic operation.

W riting to Input Latches

By keeping B1/B2 = high, a 12-bit bus has direct access to

the 12 bits of the input latches. The condition CS = WR1 =

0 loads the values contained in the data bus DB11-DB0

Table 1.

).