SC16C550 datasheet(21/52 Pages) PHILIPS

21 / 52 page

Philips Semiconductors

SC16C550

UART with 16-byte FIFO and IrDA encoder/decoder

Product data

Rev. 05 — 19 June 2003

21 of 52

9397 750 11619

7.2.1

IER versus Receive FIFO interrupt mode operation

When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1)

are enabled, the receive interrupts and register status will reﬂect the following:

• The receive data available interrupts are issued to the external CPU when the

FIFO has reached the programmed trigger level. It will be cleared when the FIFO

drops below the programmed trigger level.

• FIFO status will also be reﬂected in the user accessible ISR register when the

FIFO trigger level is reached. Both the ISR register status bit and the interrupt will

be cleared when the FIFO drops below the trigger level.

• The data ready bit (LSR[0]) is set as soon as a character is transferred from the

shift register to the receive FIFO. It is reset when the FIFO is empty.

7.2.2

IER versus Receive/Transmit FIFO polled mode operation

When FCR[0] = logic 1, resetting IER[0-3] enables the SC16C550 in the FIFO polled

mode of operation. Since the receiver and transmitter have separate bits in the LSR,

either or both can be used in the polled mode by selecting respective transmit or

receive control bit(s).

• LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.

• LSR[1-4] will provide the type of errors encountered, if any.

• LSR[5] will indicate when the transmit FIFO is empty.

• LSR[6] will indicate when both the transmit FIFO and transmit shift register are

empty.

• LSR[7] will indicate any FIFO data errors.

IER[2]

Receive Line Status interrupt. This interrupt will be issued whenever a fully

assembled receive character is transferred from RSR to the RHR/FIFO,

i.e., data ready, LSR[0].

Logic 0 = Disable the receiver line status interrupt (normal default

condition).

Logic 1 = Enable the receiver line status interrupt.

IER[1]

Transmit Holding Register interrupt. This interrupt will be issued whenever

the THR is empty, and is associated with LSR[1].

Logic 0 = Disable the transmitter empty interrupt (normal default

condition).

Logic 1 = Enable the transmitter empty interrupt.

IER[0]

Receive Holding Register interrupt. This interrupt will be issued when the

FIFO has reached the programmed trigger level, or is cleared when the

FIFO drops below the trigger level in the FIFO mode of operation.

Logic 0 = Disable the receiver ready interrupt (normal default condition).

Logic 1 = Enable the receiver ready interrupt.

Table 9:

Interrupt Enable Register bits description…continued

Bit

Symbol

Description

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