MIC45116 datasheet(18/42 Pages) MICROCHIP

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MIC45116

DS20005571A-page 18

 2016 Microchip Technology Inc.

3.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

TABLE 3-1:

PIN FUNCTION TABLE

Pin Number

Pin Name

Description

1, 2, 52

PVIN

Power Input Voltage. Connection to the drain of the internal high-side power

MOSFET. Connect an input capacitor from PVIN to PGND.

4, 44

PVDD

Supply input for the internal power MOSFET drivers. Connect PVDD pins together. Do

not leave floating.

5, 6

BST

Connection to the internal bootstrap circuitry and high-side power MOSFET drive

circuitry. Connect the two BST pins together.

8-10, 48-51

The SW pin connects directly to the switch node. Due to the high-speed switching on

this pin, the SW pin should be routed away from sensitive nodes. The SW pin also

senses the current by monitoring the voltage across the low-side MOSFET during

OFF time.

12-21

VOUT

Output Voltage. Connected to the internal inductor, the output capacitor should be

connected from this pin to PGND as close to the module as possible.

23-25, 27-30,

32-34, 40, 41

Not internally connected.

26, 31, 35, 42,

PGND

Power Ground. PGND is the return path for the step-down power module power stage.

The PGND pin connects to the source of internal low-side power MOSFET, the

negative terminals of input capacitors, and the negative terminals of output capacitors.

Signal Ground and Power Ground of MIC45116 are internally connected.

Feedback. Input to the transconductance amplifier of the control loop. The FB pin is

referenced to 0.8V. A resistor divider connecting the feedback to the output is used to

set the desired output voltage. Connect the bottom resistor from FB to system ground.

External ripple injection (series R and C) can be connected between FB and SW.

Power Good. Open-Drain Output. If used, connect to an external pull-up resistor of at

least 10 kΩ between PG and the external bias voltage.

Enable. A logic signal to enable or disable the step-down regulator module operation.

The EN pin is TTL/CMOS compatible. Logic-high = enable, logic-low = disable or

shutdown. EN pin has an internal 1 MΩ (typical) pull-down resistor to GND. Do not

leave floating.

VIN

Input for the internal linear regulator. Allows for split supplies to be used when there is

an external bus voltage available. Connect to PVIN for single supply operation.

Bypass with a 0.1 µF capacitor from VIN to PGND.

5VDD

Internal +5V Linear Regulator Output. Powered by VIN, 5VDD is the internal supply

bus for the device. In the applications with VIN < +5.5V, 5VDD should be tied to VIN to

bypass the linear regulator.

ILIM

Current Limit. Connect a resistor between ILIM and SW to program the current limit.

3, 7, 11, 22, 46

KEEPOUT Depopulated pin positions.

—VOUT ePad VOUT Exposed Pad. Internally connected to VOUT pins. Please see the PCB Layout

Guidelines section.

—

SW ePad SW Exposed Pad. Internally connected to SW pins. Please see the PCB Layout

Guidelines section.

—PGND

ePAD

PGND Exposed Pads. Please see the PCB Layout Guidelines section for the

connection to the system Ground.

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