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MCP39F511 bảng dữ liệu(PDF) 34 Page - Microchip Technology

tên linh kiện MCP39F511
Giải thích chi tiết về linh kiện  Power-Monitoring IC with Calculation and Energy Accumulation
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MCP39F511 bảng dữ liệu(HTML) 34 Page - Microchip Technology

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MCP39F511
DS20005393B-page 34
 2015 Microchip Technology Inc.
6.5.2
24-BIT ADC RESET MODE
(SOFT RESET MODE)
24-bit ADC Reset mode (also called Soft Reset) can
only
be
entered
through
setting
high
the
RESET<1:0> bits in the System Configuration Register
register. This mode is defined as the condition where
the converters are active but their output is forced to ‘0’.
6.5.3
ADC SHUTDOWN MODE
ADC Shutdown mode is defined as a state where the
converters and their biases are OFF, consuming only
leakage current. When the Shutdown bit is reset to ‘0’,
the analog biases will be enabled, as well as the clock
and the digital circuitry.
Each converter can be placed in Shutdown mode
independently. This mode is only available through
programming of the SHUTDOWN<1:0> bits in the
System Configuration Register register.
6.5.4
VREF TEMPERATURE
COMPENSATION
If desired, the user can calibrate out the temperature
drift for ultra-low VREF drift.
The internal voltage reference comprises a proprietary
circuit and algorithm to compensate first-order and
second-order
temperature
coefficients.
The
compensation allows very low temperature coefficients
(typically 10 ppm/°C) on the entire range of
temperatures from -40°C to +125°C. This temperature
coefficient varies from part to part.
The temperature coefficient can be adjusted on each
part through the System Configuration Register
register. The default value of this register is set to 0x42.
The typical variation of the temperature coefficient of
the internal voltage reference, with respect to
VREFCAL register code, is shown in Figure 6-1.
FIGURE 6-1:
VREF Tempco vs. VREFCAL
Trimcode Chart.
0
10
20
30
40
50
60
0
64
128
192
256
VREFCAL Register Trim Code (decimal)



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