MCP3913 datasheet(40/82 Pages) MICROCHIP

40 / 82 page

MCP3913

DS20005227A-page 40

 2013 Microchip Technology Inc.

5.13.2

DIGITAL GAIN ERROR

CALIBRATION

These registers are signed 24-bit MSB – first registers

coded with a range of -1x to +(1 - 2-23)x (from

0x800000 to 0x7FFFFF). The gain calibration adds 1x

to this register and multiplies it to the output code of the

channel bit by bit, after offset calibration. The range of

the gain calibration is thus from 0x to 1.9999999x (from

0x800000 to 0x7FFFFF). The LSB corresponds to

a2-23 increment in the multiplier.

Enabling EN_GAINCAL creates a pipeline delay of

24 DMCLK periods on all channels. All data ready

pulses are delayed by 24 DMCLK periods, starting

from data ready following the command enabling

EN_GAINCAL bit. The gain calibration is effective on

the next data ready following the command enabling

EN_GAINCAL bit.

The digital gain calibration does not function when the

corresponding channel is in Reset or Shutdown mode.

The gain multiplier value for an LSB in these 24-bit

registers is:

This register is a “Don't Care” if EN_GAINCAL = 0

(offset calibration disabled), but its value is not cleared

by the EN_GAINCAL bit.

The output data on each channel is kept to either 7FFF

or 8000 (16-bit mode) or 7FFFFF or 800000 (24-bit

mode) if the output results are out of bounds after all

calibrations are performed.

EQUATION 5-8:

DIGITAL OFFSET AND GAIN ERROR CALIBRATION REGISTERS

CALCULATIONS

GAIN (1LSB) = 1/8388608

DATA_CHn post

cal

–



DATA_CHn pre

cal

–

 OFFCAL_CHn



GAINCAL_CHn





MCP3913 bảng dữ liệu(PDF) 40 Page - Microchip Technology

MCP3913 bảng dữ liệu(HTML) 40 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82

bảng dữ liệu tải về

Link URL