6

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© 2002 QuickLogic Corporation

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QL4016 QuickRAM Data Sheet Rev I

Table 4: RAM Cell Asynchronous Read Timing

Symbol

Parameter

Propagation Delays (ns)

Fanout

1

2

3

4

5

RPDRD

a. Stated timing for worst case Propagation Delay over process variation at V

TA = 25

settings as specified in the Operating Range.

3.0

3.3

3.6

3.9

5.1

Table 5: Input-Only / Clock Cells

Symbol

Parameter

Propagation Delays (ns)

Fanout

1

2

3

4

8

12

24

t

IN

High Drive Input Delay

1.5

1.6

1.8

1.9

2.4

2.9

4.4

t

INI

High Drive Input, Inverting Delay

1.6

1.7

.19

2.0

2.5

3.0

4.5

Input Register Set-Up Time

3.1

3.1

3.1

3.1

3.1

3.1

3.1

t

IH

Input Register Hold Time

0.0

0.0

0.0

0.0

0.0

0.0

0.0

t

ICLK

Input Register Clock To Q

0.7

0.8

1.0

1.1

1.6

2.1

3.6

Input Register Reset Delay

0.6

0.7

0.9

1.0

1.5

2.0

3.5

t

IESU

Input Register Clock Enable Setup Time

2.3

2.3

2.3

2.3

2.3

2.3

2.3

t

IEH

Input Register Clock Enable Hold Time

0.0

0.0

0.0

0.0

0.0

0.0

0.0

Table 6: Clock Cells

Symbol

Parameter

Propagation Delays (ns)

Fanout

a

a. The array distributed networks consist of 40 half columns and the global distributed networks con-

sist of 44 half columns, each driven by an independent buffer. The number of half columns used

does not affect clock buffer delay. The array clock has up to eight loads per half column. The global

clock has up to 11 loads per half column.

1

2

3

4

8

10

11

t

ACK

Array Clock Delay

1.2

1.2

1.3

1.3

1.5

1.6

1.7

Global Clock Pin Delay

0.7

0.7

0.7

0.7

0.7

0.7

0.7

t

GCKB

Global Clock Buffer Delay

0.8

0.8

0.9

0.9

1.1

1.2

1.3