QL4016 datasheet(5/18 Pages) ETC

5 / 18 page

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QL4016 QuickRAM Data Sheet Rev I

Figure 4: QuickRAM Module

Table 2: RAM Cell Synchronous Write Timing

Symbol

Parameter

Propagation Delays (ns)

Fanout

SWA

WA Setup Time to WCLK

1.0

tHWA

WA Hold Time to WCLK

0.0

SWD

WD Setup Time to WCLK

1.0

HWD

WD Hold Time to WCLK

0.0

tSWE

WE Setup Time to WCLK

1.0

HWE

WE Hold Time to WCLK

0.0

WCRD

WCLK to RD (WA=RA)a

a. Stated timing for worst case Propagation Delay over process variation at V

CC = 3.3 V and

TA = 25

° C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature

settings as specified in the Operating Range.

5.0

5.3

5.6

5.9

7.1

Table 3: RAM Cell Synchronous Read Timing

Symbol

Parameter

Propagation Delays (ns)

Fanout

Logic Cells

tSRA

RA Setup Time to RCLK

1.0

HRA

RA Hold Time to RCLK

0.0

SRE

RE Setup Time to RCLK

1.0

tHRE

RE Hold Time to RCLK

0.0

RCRD

RCLK to RDa

a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and

TA = 25

× C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature

settings as specified in the Operating Range.

4.0

4.3

4.6

4.9

6.1

WCLK

RCLK

[8:0]

[17:0]

[8:0]

[17:0]

MODE

ASYNCRD

[1:0]

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