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XRA00 bảng dữ liệu(PDF) 14 Page - STMicroelectronics

tên linh kiện XRA00
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XRA00 bảng dữ liệu(HTML) 14 Page - STMicroelectronics

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Figure 19. Transmission of XRA00 Answers
XRA00 Answer Bit Cell Variation. Durind
the
Reader Request Frame command, the XRA00
synchronizes its internal PLL (Phase Lock Loop)
to the Master Clock Time Period, t0, generated by
the Reader. Due to the internal PLL drift in the
XRA00, the answer data bit cell period ttagbitcell
may vary by up to ±1/8t0.
Figure 20. XRA00 Answer Bit Cell Variation
Table 4. XRA00 Backscattered Answer Modulation Parameters
ai10758
100%
100%
Symbol
Description
Min
Max
Units
t0
Master Clock Time Period for a single bit sent to the
XRA00
North American Operation
12.5
16.6
µs
Master Clock Time Period for a single bit sent to the
XRA00
European Operation Preliminary Data
40
66.67
µs
ttagbitcell
XRA00 to Reader data bit cell period
1/2 x t0
µs
ttagbitcellTol
XRA00 to Reader data bit cell period Tolerance
(measured on 96+16+8 bits)
±1/8 x t0
µs
2 / t0
Answer Frame Data Rate (2/t0) for North American Operation
120
160
kbps
Answer Frame Data Rate (2/t0) for European Operation
Preliminary Data
30
50
kbps
ttagbitcell
Nominal Symbol at Start of Reply
Fast (
−1/8t0) Symbol
Slow (+1/8t0) Symbol
−1/8t0
+1/8t0
ai10759



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