TMS416400, TMS416400P, TMS417400, TMS417400P

TMS426400, TMS426400P, TMS427400, TMS427400P

4194304-WORD BY 4-BIT HIGH-SPEED DRAMS

SMKS881B – MAY 1995 – REVISED AUGUST 1995

3

POST OFFICE BOX 1443

RAS-only refresh

TMS4x6400, TMS4x6400P

A refresh operation must be performed at least once every 64 ms (128 ms for TMS4x6400P) to retain data. This

can be achieved by strobing each of the 4096 rows (A0 – A11). A normal read or write cycle refreshes all bits

in each row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level,

conserving power as the output buffers remain in the high-impedance state. Externally generated addresses

must be used for a RAS-only refresh.

TMS4x7400, TMS4x7400P

A refresh operation must be performed at least once every 32 ms (128 ms for TMS4x7400P) to retain data. This

can be achieved by strobing each of the 2048 rows (A0 – A10). A normal read or write cycle refreshes all bits

in each row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level,

conserving power as the output buffers remain in the high-impedance state. Externally generated addresses

must be used for a RAS-only refresh.

hidden refresh

Hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by holding

refresh cycle. The external address is ignored, and the refresh address is generated internally.

CAS-before-RAS ( CBR ) refresh

external address is ignored, and the refresh address is generated internally.

battery-backup refresh

TMS4x6400P

A low-power battery-backup refresh mode that requires less than 500

µA (5 V) or 350 µA (3.3 V) refresh current

is available on the TMS4x6400P. Data integrity is maintained using CBR refresh with a period of 31.25

µs while

holding RAS low for less than 1

µs. To minimize current consumption, all input levels must be at CMOS levels

TMS4x7400P

A low-power battery-backup refresh mode that requires less than 500

µA (5 V) or 350 µA (3.3 V) refresh current

is available on the TMS4x7400P. Data integrity is maintained using CBR refresh with a period of 62.5

µs while

holding RAS low for less than 1

µs. To minimize current consumption, all input levels must be at CMOS levels

self refresh ( TMS4xx400P)

The self-refresh mode is entered by dropping CAS low prior to RAS going low. Then CAS and RAS are both

held low for a minimum of 100

µs. The chip is then refreshed internally by an on-board oscillator. No external

address is required because the CBR counter is used to keep track of the address. To exit the self-refresh mode,

full set of row addresses) must be executed before continuing with normal operation. The burst refresh ensures

the DRAM is fully refreshed.

power up

To achieve proper device operation, an initial pause of 200

µs followed by a minimum of eight initialization cycles

( RAS-only or CBR ) cycle.