TMS320C6411 datasheet(81/119 Pages) TI

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TMS320C6411

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS196H − MARCH 2002 − REVISED JULY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

PROGRAMMABLE SYNCHRONOUS INTERFACE TIMING (CONTINUED)

ECLKOUTx

CEx

BE[3:0]

EA[22:3]

ED[31:0]

ARE/SDCAS/SADS/SRE§

AOE/SDRAS/SOE§

AWE/SDWE/SWE§

BE1

BE2

BE3

BE4

EA1

EA2

EA3

EA4

Write

Latency =

1†

† The write latency and the length of CEx assertion are programmable via the SYNCWL and CEEXT fields, respectively, in the EMIF CE Space

Secondary Control register (CExSEC). In this figure, SYNCWL = 1 and CEEXT = 0.

‡ The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):

− Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency

− Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency

− CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, CEx goes inactive after the final command has been issued

(CEEXT = 0). For synchronous FIFO interface with glue, CEx is active when SOE is active (CEEXT = 1).

− Function of SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, SADS/SRE acts as SADS with deselect cycles

(RENEN = 0). For FIFO interface, SADS/SRE acts as SRE with NO deselect cycles (RENEN = 1).

− Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2

§ ARE/SDCAS/SADS/SRE, AOE/SDRAS/SOE, and AWE/SDWE/SWE operate as SADS/SRE, SOE, and SWE, respectively, during

programmable synchronous interface accesses.

Figure 26. Programmable Synchronous Interface Write Timing (With Write Latency = 1)†‡

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