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ST7MC1K2TC bảng dữ liệu(PDF) 44 Page - STMicroelectronics

tên linh kiện ST7MC1K2TC
Giải thích chi tiết về linh kiện  8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, BRUSHLESS MOTOR CONTROL, FIVE TIMERS, SPI, LINSCI
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
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ST7MC1K2TC bảng dữ liệu(HTML) 44 Page - STMicroelectronics

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INTERRUPTS (Cont’d)
7.6 EXTERNAL INTERRUPTS
The pending interrupts are cleared writing a differ-
ent value in the ISx[1:0], IPA or IPB bits of the
EICR.
Note: External interrupts are masked when an I/O
(configured as input interrupt) of the same inter-
rupt vector is forced to VSS.
7.6.1 I/O PORT INTERRUPT SENSITIVITY
The external interrupt sensitivity is controlled by
the IPA, IPB and ISxx bits of the EICR register
(Figure 24). This control allows to have up to 4 fully
independent external interrupt source sensitivities.
Each external interrupt source can be generated
on four (or five) different events on the pin:
■ Falling edge
■ Rising edge
■ Falling and rising edge
■ Falling edge and low level
■ Rising edge and high level (only for ei0 and ei2)
To guarantee correct functionality, the sensitivity
bits in the EICR register can be modified only
when the I1 and I0 bits of the CC register are both
set to 1 (level 3).
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