ST7MC1K2TC datasheet(41/308 Pages) STMICROELECTRONICS

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ST7MC1/ST7MC2

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INTERRUPTS (Cont’d)

7.3 INTERRUPTS AND LOW POWER MODES

All interrupts allow the processor to exit the WAIT

low power mode. On the contrary, only external

and other specified interrupts allow the processor

to exit from the HALT modes (see column “Exit

from HALT” in “Interrupt Mapping” table). When

several pending interrupts are present while exit-

ing HALT mode, the first one serviced can only be

an interrupt with exit from HALT mode capability

and it is selected through the same decision proc-

ess shown in Figure 21.

Note: If an interrupt, that is not able to Exit from

HALT mode, is pending with the highest priority

when exiting HALT mode, this interrupt is serviced

after the first one serviced.

7.4 CONCURRENT & NESTED MANAGEMENT

The following Figure 22 and Figure 23 show two

different interrupt management modes. The first is

called concurrent mode and does not allow an in-

terrupt to be interrupted, unlike the nested mode in

Figure 23. The interrupt hardware priority is given

in this order from the lowest to the highest: MAIN,

IT4, IT3, IT2, IT1, IT0, MCES. The software priority

is given for each interrupt.

Warning: A stack overflow may occur without no-

tifying the software of the failure.

Figure 22. Concurrent Interrupt Management

Figure 23. Nested Interrupt Management

MAIN

IT4

IT2

IT1

MCES

IT1

MAIN

IT0

SOFTWARE

3/0

11 / 10

RIM

IT3

PRIORITY

LEVEL

MAIN

IT2

MCES

MAIN

IT0

3/0

RIM

IT1

IT4

IT1

IT2

IT3

11 / 10

SOFTWARE

PRIORITY

LEVEL

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