EMC1182 datasheet(33/48 Pages) MICROCHIP

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Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications

Datasheet

SMSC EMC1182

Revision 1.0 (07-11-13)

DATASHEET

6.11

Consecutive ALERT Register 22h

The Consecutive ALERT Register determines how many times an out-of-limit error or diode fault must

be detected in consecutive measurements before the ALERT / THERM2 or THERM pin is asserted.

Additionally, the Consecutive ALERT Register controls the SMBus Timeout functionality.

An out-of-limit condition (i.e. HIGH, LOW, or FAULT) occurring on the same temperature channel in

consecutive measurements will increment the consecutive alert counter. The counters will also be reset

if no out-of-limit condition or diode fault condition occurs in a consecutive reading.

When the ALERT / THERM2 pin is configured as an interrupt, when the consecutive alert counter

reaches its programmed value, the following will occur: the STATUS bit(s) for that channel and the last

error condition(s) (i.e. EHIGH) will be set to ‘1’, the ALERT / THERM2 pin will be asserted, the

consecutive alert counter will be cleared, and measurements will continue.

When the ALERT / THERM2 pin is configured as a comparator, the consecutive alert counter will

ignore diode fault and low limit errors and only increment if the measured temperature exceeds the

High Limit. Additionally, once the consecutive alert counter reaches the programmed limit, the ALERT/

THERM2 pin will be asserted, but the counter will not be reset. It will remain set until the temperature

drops below the High Limit minus the Therm Hysteresis value.

For example, if the CALRT[2:0] bits are set for 4 consecutive alerts on an EMC1182 device, the high

limits are set at 70°C, and none of the channels are masked, the ALERT / THERM2 pin will be

asserted after the following four measurements:

1. Internal Diode reads 71°C and the external diode reads 69°C. Consecutive alert counter for INT is

incremented to 1.

2. Both the Internal Diode and the External Diode read 71°C. Consecutive alert counter for INT is

incremented to 2 and for EXT is set to 1.

3. The External Diode reads 71°C and the Internal Diode reads 69°C. Consecutive alert counter for

INT is cleared and EXT is incremented to 2.

4. The Internal Diode reads 71°C and the external diode reads 71°C. Consecutive alert counter for

INT is set to 1 and EXT is incremented to 3.

5. The Internal Diode reads 71°C and the external diode reads 71°C. Consecutive alert counter for

INT is incremented to 2 and EXT is incremented to 4. The appropriate status bits are set for EXT

and the ALERT / THERM2 pin is asserted. EXT counter is reset to 0 and all other counters hold

the last value until the next temperature measurement.

Bit 7 - TIMEOUT - Determines whether the SMBus Timeout function is enabled.



‘0’ (default) - The SMBus Timeout feature is disabled. The SMCLK line can be held low indefinitely

without the device resetting its SMBus protocol.



‘1’ - The SMBus Timeout feature is enabled. If the SMCLK line is held low for more than tTIMEOUT,

the device will reset the SMBus protocol.

Bits 6-4 CTHRM[2:0] - Determines the number of consecutive measurements that must exceed the

corresponding Therm Limit and Hardware Thermal Shutdown Limit before the SYS_SHDN pin is

asserted. All temperature channels use this value to set the respective counters. The consecutive

THERM counter is incremented whenever any of the measurements exceed the corresponding Therm

Limit or if the External Diode measurement exceeds the Hardware Thermal Shutdown Limit.

Table 6.11 Consecutive ALERT Register

ADDR.

R/W

DEFAULT

22h

R/W

Consecutive

ALERT

TIME

OUT

CTHRM[2:0]

CALRT[2:0]

70h

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