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EMC1183 bảng dữ liệu(PDF) 34 Page - Microchip Technology |
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EMC1183 bảng dữ liệu(HTML) 34 Page - Microchip Technology |
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34 / 48 page ![]() Triple Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet Revision 1.0 (07-11-13) 34 SMSC EMC1183 DATASHEET The External Diode Fault Register indicates which of the external diodes caused the FAULT bit in the Status Register to be set. This register is cleared when it is read. Bit 2 - E2FLT - This bit is set if the External Diode 2 channel reported a diode fault. Bit 1 - E1FLT - This bit is set if the External Diode 1 channel reported a diode fault. 6.11 Channel Mask Register 1Fh The Channel Mask Register controls individual channel masking. When a channel is masked, the ALERT / THERM2 pin will not be asserted when the masked channel reads a diode fault or out of limit error. The channel mask does not mask the THERM pin. Bit 2 - E2MASK - Masks the ALERT pin from asserting when the External Diode 2 channel is out of limit or reports a diode fault. ‘0’ (default) - The External Diode 2 channel will cause the ALERT / THERM2pin to be asserted if it is out of limit or reports a diode fault. ‘1’ - The External Diode 2 channel will not cause the ALERT / THERM2 pin to be asserted if it is out of limit or reports a diode fault. Bit 1 - E1MASK - Masks the ALERT / THERM2 pin from asserting when the External Diode 1 channel is out of limit or reports a diode fault. ‘0’ (default) - The External Diode 1 channel will cause the ALERT / THERM2 pin to be asserted if it is out of limit or reports a diode fault. ‘1’ - The External Diode 1 channel will not cause the ALERT / THERM2 pin to be asserted if it is out of limit or reports a diode fault. Bit 0 - INTMASK - Masks the ALERT / THERM2 pin from asserting when the Internal Diode temperature is out of limit. ‘0’ (default) - The Internal Diode channel will cause the ALERT / THERM2 pin to be asserted if it is out of limit. ‘1’ - The Internal Diode channel will not cause the ALERT / THERM2 pin to be asserted if it is out of limit. 6.12 Consecutive ALERT Register 22h Table 6.12 Channel Mask Register ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 1Fh R/W Channel Mask - --- - E2 MASK E1 MASK INT MASK 00h Table 6.13 Consecutive ALERT Register ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 22h R/W Consecutive ALERT TIME OUT CTHRM[2:0] CALRT[2:0] - 70h |
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