UCD3138 datasheet(62/89 Pages) TI1

62 / 89 page

2 B – QB2

( EDGEGEN )

2 A – QT 2

( EDGEGEN )

0 B –

QSYN 2,4

1 B –

QSYN 1,3

X1 , X2 , X 3 and Y 1 , Y2 , Y 3

are sets of moving edges

All other edges are fixed .

DPWM 2 AF

DPWM 2 BF

DPWM 3 AF

DPWM 3 BF

Current

Peak Level

3 A – QB1

( DPWM 1 C)

3 B – QT1

( DPWM 2 C)

Period Start

Period End

Chopping point

Y 1

UCD3138

SLUSAP2G – MARCH 2012 – REVISED SEPTEMBER 2016

www.ti.com

Submit Documentation Feedback

Product Folder Links: UCD3138

Application and Implementation

Figure 7-6. Dynamic Signals to Bridge

The Edge Generator is configured with these statements:

Dpwm2Regs.DPWMEDGEGEN.bit.A_ON_EDGE = 2;

Dpwm2Regs.DPWMEDGEGEN.bit.A_OFF_EDGE = 5;

Dpwm2Regs.DPWMEDGEGEN.bit.B_ON_EDGE = 6;

Dpwm2Regs.DPWMEDGEGEN.bit.B_OFF_EDGE = 1;

Dpwm2Regs.DPWMCTRL0.bit.PWM_A_INTRA_MUX = 1; // EDGEGEN-A out the A output

Dpwm2Regs.DPWMCTRL0.bit.PWM_B_INTRA_MUX = 1; // EDGEGEN-B out the B output

Dpwm2Regs.DPWMEDGEGEN.bit.EDGE_EN = 1;

The EDGE_EN bits are set for all 4 DPWMs. This is done to ensure that all signals have the same timing

delay through the DPWM.

The finial 6 gate signals are shown in Figure 7-7.

UCD3138 bảng dữ liệu(PDF) 62 Page - Texas Instruments

UCD3138 bảng dữ liệu(HTML) 62 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89

bảng dữ liệu tải về

Link URL