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PCA9846PW bảng dữ liệu(PDF) 9 Page - NXP Semiconductors |
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PCA9846PW bảng dữ liệu(HTML) 9 Page - NXP Semiconductors |
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9 / 32 page ![]() PCA9846 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 1 — 9 November 2015 9 of 32 NXP Semiconductors PCA9846 4-channel ultra-low voltage, Fm+ I2C-bus switch with reset 6.3 Control register Following the successful acknowledgement of the slave address, the bus master will send a byte to the PCA9846, which will be stored in the control register. If multiple bytes are received by the PCA9846, it will save the last byte received. This register can be written and read via the I2C-bus. If more than 3 bytes are read, the slave device loops back to the first byte (manufacturer byte) and keeps sending data until the master generates a ‘no acknowledge’. Fig 9. Device ID field read operation aaa-011781 A7 A6 A5 A4 A3 A2 A1 I2C-bus slave address of the device to be identified A no acknowledge from master P STOP condition M 11 M 10 M9 M8 M7 M6 M5 M4 Sr repeated START condition 1 A R/W S 1 1 1 1 1 0 0 Device ID address START condition 0 A R/W acknowledge from one or several slaves 0 A don’t care acknowledge from slave to be identified 1 1 1 1 1 0 0 Device ID address acknowledge from slave to be identified A M3 M2 M1 M0 acknowledge from master manufacturer name = 000000000000 P8 P7 P6 P5 A acknowledge from master P4 P3 P2 P1 P0 R2 R1 R0 part identification = 100001010 revision = 000 Fig 10. Control register 002aab190 X X X X B3 B2 B1 B0 channel selection bits (read/write) 76543210 channel 0 channel 1 channel 2 channel 3 |
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