STV6889 datasheet(47/56 Pages) STMICROELECTRONICS

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STV6889

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9.8.2

Composite output HLckVBk

The composite output HLckVBk provides, at the

same time, information about lock state of PLL1

and early vertical blanking pulse. As both signals

have two logical levels, a four level signal is used

to define the combination of the two. Schematic di-

agram putting together all safety functions and

composite PLL1 lock and V-blanking indication is

in Figure 17, the combinations, their respective lev-

els and the HLckVBk configuration in Figure 18.

The early vertical blanking pulse is obtained by a

logic combination of vertical synchronization pulse

and pulse corresponding to vertical oscillator dis-

charge. The combination corresponds to the draw-

ing in Figure 18. The blanking pulse is started with

the leading edge of any of the two signals, which-

ever comes first. The blanking pulse is ended with

the trailing edge of vertical oscillator discharge

pulse. The device has no information about the

vertical retrace time. Therefore, it does not cover,

by the blanking pulse, the whole vertical retrace

period. By means of BlankMode I²C-bus bit, when

at 1 (default), the blanking level (one of two ac-

cording to PLL1 status) is made available on the

HLckVBk

permanently. The permanent blanking, ir-

respective of the BlankMode I²C-bus bit, is also

provided if the supply voltage is low (under VCCEn

or VCCDis thresholds), if the X-ray protection is ac-

tive or if the V-drive signal is disabled by VOutEn

I²C-bus bit.

Figure 18. Levels on HLckVBk composite output

HPLL1 locked

V-early blanking

Yes

L1(H)+L2(L)

L1(L)+L2(H)

L1(H)+L2(H)

L1(L)+L2(L)

L1 - No blank/blank level

L2 - H-lock/unlock level

HLckVBk

VCC

VOLckBk

ISinkLckBk

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