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HT95A400 bảng dữ liệu(PDF) 14 Page - Holtek Semiconductor Inc

tên linh kiện HT95A400
Giải thích chi tiết về linh kiện  I/O Type Phone 8-Bit MCU
PDF  48 Pages
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nhà sản xuất  HOLTEK [Holtek Semiconductor Inc]
Trang chủ  http://www.holtek.com
Logo HOLTEK - Holtek Semiconductor Inc

HT95A400 bảng dữ liệu(HTML) 14 Page - Holtek Semiconductor Inc

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HT95AXXX
Rev. 1.20
14
May 26, 2004
The WDT OSC period is 78
ms. This time-out period may
vary with temperature, VDD and process variations. The
WDT OSC always works for any operation mode.
If the instruction clock is selected as the WDT clock
source, the WDT operates in the same manner except in
the Sleep mode or Idle mode. In these two modes, the
WDT stops counting and lose its protecting purpose. In
this situation the logic can only be re-started by external
logic.
If the WDT clock source is the 32768Hz, the WDT also
operates in the same manner except in the Idle mode.
When in the Idle mode, the 32768Hz stops, the WDT
stops counting and lose its protecting purpose. In this
situation the logic can only be re-started by external
logic.
The high nibble and bit3 of the WDTS are reserved for
user defined flags, which can be used to indicate some
specified status.
The WDT time-out under Normal mode or Green mode
will initialize
²chip reset² and set the status bit ²TO². But
in the Sleep mode or Idle mode, the time-out will initial-
ize a
²warm reset² and only the program counter and
stack pointer are reset to 0. To clear the WDT contents
(including the WDT prescaler), three methods are
adopted; external reset (a low level to RES pin), soft-
ware instruction and a
²HALT² instruction.
The software instruction include
²CLR WDT² and the
other set
²CLR WDT1² and ²CLR WDT2². Of these two
types of instruction, only one can be active depending
on the mask option
²WDT instr².Ifthe ²CLR WDT² is se-
lected (i.e. One clear instruction), any execution of the
CLR WDT instruction will clear the WDT. In the case that
²CLR WDT1² and ²CLR WDT2² are chosen (i.e. Two
clear instructions), these two instructions must be exe-
cuted to clear the WDT; otherwise, the WDT may reset
the chip as a result of time-out.
Controller Operation Mode
Holtek
¢s telephone controllers support two system clock
and four operation modes. The system clock could be
32768Hz or 3.58MHz and operation mode could be Nor-
mal, Green, Sleep or Idle mode. These are all selected
by the software.
The following conditions will force the operation mode to
change to Green mode:
· Any reset condition from any operation mode
· Any interrupt from Sleep mode or Idle mode
· Port A wake-up from Sleep mode or Idle mode
How to change the Operation Mode
· Normal mode to Green mode:
Clear MODE1 to 0, then operation mode is changed to
Green mode but the UPEN status is not changed.
However, UPEN can be cleared by software.
· Normal mode or Green mode to Sleep mode:
Step 1: Clear MODE0 to 0
Step 2: Clear MODE1 to 0
Step 3: Clear UPEN to 0
Step 4: Execute HALT instruction
After Step 4, operation mode is changed to Sleep
mode.
· Normal mode or Green mode to Idle mode:
Step 1: Set MODE0 to 1
Step 2: Clear MODE1 to 0
Step 3: Clear UPEN to 0
Step 4: Execute HALT instruction
After Step 4, operation mode is changed to Idle mode.
Register
Label
Bits
R/W
Function
MODE
(26H)
¾
4~0
RO
Unused bit, read as
²0²
UPEN
5
RW
1: Enable frequency up conversion function to generate 3.58MHz
0: Disable frequency up conversion function to generate 3.58MHz
MODE0
6
RW
1: Disable 32768Hz oscillator while the HALT instruction is executed
(Idle mode)
0: Enable 32768Hz oscillator while the HALT instruction is executed
(Sleep mode)
MODE1
7
RW
1: Select 3.58MHz as CPU system clock
0: Select 32768Hz as CPU system clock
Operation Mode Description
HALT
Instruction
MODE1
MODE0
UPEN
Operation
Mode
32768Hz
3.58MHz
System
Clock
Not execute
1
X
1
Normal
ON
ON
3.58MHz
Not execute
0
X
0
Green
ON
OFF
32768Hz
Be executed
0
0
0
Sleep
ON
OFF
HALT
Be executed
0
1
0
Idle
OFF
OFF
HALT
Note:
²X² means don¢t care



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