SLMA002 datasheet(14/46 Pages) TI1

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DELAY

ENx

farads

2 I

(1)

TPS5538x

ENx

VDD2

VDDx

5 mA

1.25 V

Time

DELAY

PVDDx

ENx

OUTx

1.2-V

Threshold

Output Voltage Sequencing

TPS55383

,, TPS55386

SLUS818 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com

where:

• R and C are the timing components

• V

TH is the 1.2-V enable threshold voltage

• I

ENx is the 6 µA enable pin biasing current

Additional enable pin functionality is dictated by the state of the SEQ pin. (See the Output Voltage Sequencing

section.)

Figure 16. Startup Delay Schematic

Figure 17. Startup Delay with R-C on Enable

DESIGN HINT

If delayed output voltage startup is not necessary, simply connect EN1 and EN2 to

GND. This configuration allows the outputs to start immediately on valid application of

PVDD2.

If ENx is allowed to go high after the Outputx has been in regulation, the upper MOSFET shuts off, and the

output decays at a rate determined by the output capacitor and the load. The internal pulldown MOSFET remains

in the OFF state. (See the Bootstrap for N-Channel MOSFET section.)

The TPS5538x allows single-pin programming of output voltage startup sequencing. During power-on, the state

of the SEQ pin is detected. Based on whether the pin is tied to BP, to GND, or left floating, the outputs function

as described in Table 1.

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