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VSP1221 bảng dữ liệu(PDF) 18 Page - Texas Instruments

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tên linh kiện VSP1221
Giải thích chi tiết về linh kiện  12-BIT, 21-MSPS, ULTRALOW-POWER CCD SIGNAL PROCESSOR
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Trang chủ  http://www.ti.com
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VSP1221 bảng dữ liệu(HTML) 18 Page - Texas Instruments

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STANDBY (POWER-DOWN MODE)
GENERAL PURPOSE DAC
VSP1221
SLES012A – SEPTEMBER 2001 – REVISED JULY 2004
PRINCIPLES OF OPERATION (continued)
To save power, the VSP1221 can be put into standby mode (power-down mode) both through hardware and
software. Pulling the STBY signal low puts the device into standby mode (hardware power-down). In this mode,
the reference is pulled down, all the functional blocks are disabled, the output is all zero, and the power
dissipation is zero. The power-up time is of the order of 10 ms. Software power down can be exercised by
resetting the STBYZ bit in the control register through the serial port (see the control register section). This is
similar to hardware power down, except that the reference is not pulled down. Hence, the power dissipation is
around 4 mW and the power-up time is of the order of 10 µs. The user can still program all the internal registers
during both hardware and software power down.
The VSP1221 has two 8-bit general-purpose digital-to-analog converters (DACs) that can be used for external
analog settings. The output voltage of each DAC can be independently set and has a range of 0 V to the supply
voltage with eight-bit resolution. The digital input to the DACs can be set by programming the User DAC1 and
User DAC2 registers through the serial port (see the User DAC1 register and User DAC2 register sections).
When not used in the system, the DACs can be put in standby mode by programming the above-mentioned
registers. The DACs are, by default, in standby mode. The average power consumed by each DAC is
approximately 1 mW.
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