LM4950TS datasheet(19/25 Pages) NSC

19 / 25 page

Application Information (Continued)

and an

L = 20kHzx5= 100kHz

(13)

As mentioned in the SELECTING EXTERNAL COMPO-

NENTS section, R

INA and CINA create a highpass filter that

sets the amplifier’s lower bandpass frequency limit. Find the

coupling capacitor’s value using Equation (14).

i =1 / 2

πR

INfL

(14)

The result is

1 / (2

πx20kΩx10Hz) = 0.795µF

Use a 0.82µF capacitor, the closest standard value.

The product of the desired high frequency cutoff (100kHz in

this example) and the differential gain A

VD, determines the

upper passband response limit. With A

VD = 7 and fH =

100kHz, the closed-loop gain bandwidth product (GBWP) is

700kHz. This is less than the LM4950’s 3.5MHz GBWP. With

this margin, the amplifier can be used in designs that require

more differential gain while avoiding performance restricting

bandwidth limitations.

RECOMMENDED PRINTED CIRCUIT BOARD LAYOUT

Figure 5 through Figure 7 show the recommended two-layer

PC board layout that is optimized for the TO263-packaged,

SE-configured LM4950 and associated external compo-

nents. Figure 8 through Figure 10 show the recommended

two-layer PC board layout that is optimized for the TO263-

packaged, BTL-configured LM4950 and associated external

components. These circuits are designed for use with an

external 12V supply and 4

Ω(min)(SE) or 8Ω(min)(BTL)

speakers.

These circuit boards are easy to use. Apply 12V and ground

to the board’s V

DD and GND pads, respectively. Connect a

speaker between the board’s OUT

A and OUTBoutputs.

Demonstration Board Layout

20047063

FIGURE 5. Recommended TS SE PCB Layout:

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