HV2802 datasheet(15/26 Pages) MICROCHIP

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 2015 Microchip Technology Inc.

DS20005449A-page 15

HV2802/HV2902

FIGURE 4-2:

Latch Enable Timing Waveforms.

When the CLR input is set high, all 32 latches are

cleared of the data. Consequently, all the high-voltage

switches are set to off state. However, the CLR signal

does not affect the contents of the shift register, so the

shift register can operate independently of the CLR

signal. Hence, after the CLR input is set low, the shift

The serial input interface of the HV2802/HV2902

allows multiple devices to daisy-chain together. In this

configuration, DOUT of a HV2802/HV2902 device is

connected to the DIN of the subsequent device, and so

forth.

The

last

DOUT of the daisy-chained

HV2802/HV2902 can either be floating or fed back to

an FPGA to check the previously stored shift register

data. To control all the high-voltage analog switch

states in daisy-chained N devices, N times 32 clocks

and N times 32 bits of data are shifted into shift

registers, while LE remains high and CLR remains low.

After all N times 32 bits of data finish shifting in, the

high-to-low transition of the LE transfers the data from

all N times 32-bit shift registers to N times 32 latches

simultaneously.

Consequently,

all

times

high-voltage

analog

switches

change

states

simultaneously.

It is recommended that 0.1 uF ceramic decoupling

capacitors, with the appropriate voltage ratings, be

connected between GND and the other supplies (VDD,

VPP and VNN). These decoupling capacitors should be

placed as close as possible to the device.

The HV2802/HV2902 devices do not have a specific

power up/down sequence. During the power up/down

period, all the analog switch inputs should be within the

VPP and VNN range or floating. The rise time and fall

time of the power supplies, VDD, VPP and VNN, should

be greater than 1 ms. Violating the rise time or fall time

requirement on the power supplies may cause

malfunction such as latch-up or even permanent

damage of the device.

The HV2902 device has 35 k

 integrated bleed

resisters connected from all the analog switch

terminals A and B to RGND. These bleed resisters

eliminate voltage build-up on capacitive loads such as

piezoelectric transducers. The HV2802 device does

not have integrated bleed resistors.

DIN

CLK

tWLE

tSD

tSU

tDO

DOUT

N-1

*The previous data input in the shift register are shifted out

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