MCP19116-ESLASHMJ datasheet(20/246 Pages) MICROCHIP

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MCP19116/7

DS20005479B-page 20

 2015-2016 Microchip Technology Inc.

3.6

Start-Up

To control the output current during start-up, the

MCP19116/7 devices have the capability to monotoni-

cally increase system current at the user’s discretion.

This is accomplished through the control of the refer-

ence voltage DAC (VREF). Users also have firmware

control over the switching frequency through Timer2

and the PR2 register. Maximum duty-cycle control is

established through the PWMRL register. Refer to

Section 26.0, Enhanced PWM Module for details. The

entire start-up profile is under user control via software.

3.7

Driver Control Circuitry

The internal driver control circuitry of the MCP19116/7

is comprised of an error amplifier (EA), a high-speed

comparator and a latch similar to the MCP1631.

The error amplifier generates the control voltage used

by the high-speed PWM comparator. There is an

internally generated reference voltage, VREF. The

difference or error between this internal reference

voltage and the actual feedback voltage is the control

voltage. Some applications will implement parked

times where the gate drives are not active. For

example, when changing between LED strings and

after voltage repositioning, the user can disable the

gate drives and park the error amplifier output low.

During the time when the EA is parked, its output will be

clamped low (1 * BG) such that it is in a known state

when reactivated. Before the output switches are

re-enabled, it may be necessary to re-enable the EA

some time prior to enabling the output drivers. This

prior-EA enable time will allow the EA to slew towards

the intended target and prevent the secondary switch

from turning on for an extensive period of time,

unintentionally discharging the output capacitance and

pulling

the

output

voltage

down.

External

compensation is used to stabilize the control system.

Since the MCP19116/7 devices are peak current mode

controlled, the comparator compares the primary peak

current waveform (IP) that is based upon the current

flowing in the primary side with the error amplifier

control output voltage. This error amplifier control

output voltage also has user-programmable slope

compensation subtracted from it. In fixed-frequency

applications, the slope compensation signal is

generated to be greater than 1/2 the down slope of the

inductor current waveform and is controlled by the

SLPCRCON register. Offset adjust ability is also

available to set the peak current limit of the primary

switch for overcurrent protection. The range of the

slope compensation ramp is specified. When the

current sense signal reaches the level of the control

voltage minus slope compensation, the ON cycle is

terminated and the external PDRV switch is latched off

until the beginning of the next cycle which begins at the

next clock cycle.

To improve current regulation at low levels, a pedestal

voltage (VZC) set to the BG (1.23V) is implemented.

This virtual ground serves as the reference for the error

amplifier (A1), slope compensation, current sense

amplifier (A2) and the IP offset adjustment.

An S-R latch (Set-Rest-Flip-Flop) is used to prevent the

PWM circuitry from turning the external switch on until

the beginning of the next clock cycle.

3.8

Fixed PWM Frequency

The switching frequency of the MCP19116/7 while not

controlled by the DESAT comparator output is

generated by using a single edge of the 8 MHz internal

clock. The user sets the MCP19116/7 switching

frequency by configuring the PR2 register. The

maximum allowable PDRV duty cycle is adjustable and

controlled

the

PWMRL

The

programmable range of the switching frequency will be

31.25 kHz to 2 MHz. The available switching frequency

below 2 MHz is defined as FSW = 8 MHz/N, where N is

a whole number between 4

 N  256. Refer to

Section 26.0 “Enhanced PWM Module” for details.

3.9

VREF

This reference is used to generate the voltage

connected to the non-inverting input of the error

amplifier. The entire analog control loop is raised to a

virtual ground pedestal equal to the Band Gap voltage

(1.23V).

3.10

OV REF

This reference is used to set the output overvoltage set

point. It is compared to the VS input pin, which is

typically proportional to the output voltage based on a

resistor divider. OV protection, when enabled, can be

set to a value for the protection of system circuitry, or it

can be used to “ripple” regulate the converter output

voltage for repositioning purposes. For details, refer to

3.11

Independent Gate Drive with

Programmable Delay

Two independent low-side gate drives are integrated

for synchronous applications. Programmable delay has

been implemented to improve efficiency and prevent

shoot-through currents. Each gate drive has an

independent enable input controlled by the PE1

DEADCON register.

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