TMS320UC5409 datasheet(8/81 Pages) TI1

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TMS320UC5409

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS101E − APRIL 1999 − REVISED OCTOBER 2008

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

terminal functions

The following table lists each signal, function, and operating mode(s) grouped by function.

Terminal Functions

TERMINAL

NAME

I/O†

DESCRIPTION

TERMINAL

NAME

I/O†

DESCRIPTION

DATA SIGNALS

A22

(MSB)

A21

A20

A19

A18

A17

A16

O/Z

Parallel address bus A22 [most significant bit (MSB)] through A0 [least significant bit (LSB)]. The lower sixteen

address pins (A0 to A15) are multiplexed to address all external memory (program, data) or I/O while the upper seven

address pins (A16 to A22) are only used to address external program space. These pins are placed in the

high-impedance state when the hold mode is enabled, or when OFF is low.

A16

A15

A14

A13

A12

A11

A10

(LSB)

A15

(MSB)

A14

A13

A12

A11

A10

(LSB)

These pins can be used to address internal memory via the HPI when the HPI16 pin

is high (A0 – A15).

D15

(MSB)

D14

D13

D12

D11

D10

I/O/Z

D15

(MSB)

D14

D13

D12

D11

D10

I/O

Parallel data bus D15 (MSB) through D0 (LSB). The sixteen data pins (D0 to D15) are

multiplexed to transfer data between the core CPU and external data/program

memory or I/O devices. The data bus is placed in the high-impedance state when not

outputting or when RS or HOLD is asserted. The data bus also goes into the

high-impedance state when OFF is low.

The data bus has bus holders to reduce the static power dissipation caused by

floating, unused pins. These bus holders also eliminate the need for external bias

(LSB)

floating, unused pins. These bus holders also eliminate the need for external bias

resistors on unused pins. When the data bus is not being driven by the UC5409, the

bus holders keep the pins at the previous logic level. The data bus holders on the

UC5409 are disabled at reset and can be enabled/disabled via the BH bit of the

bank-switching control register (BSCR).

INITIALIZATION, INTERRUPT, AND RESET OPERATIONS

IACK

O/Z

Interrupt acknowledge signal. IACK indicates receipt of an interrupt and that the program counter is fetching the

interrupt vector location designated by A15−A0. IACK also goes into the high-impedance state when OFF is low.

INT0

INT1

INT2

INT3

External user interrupts. INT0−INT3 are prioritized and are maskable by the interrupt mask register and the interrupt

mode bit. INT0 −INT3 can be polled and reset by way of the interrupt flag register.

NMI

Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM or the IMR. When

NMI is activated, the processor traps to the appropriate vector location.

† I = Input, O = Output, Z = High-impedance, S = Supply

‡ Although this pin includes an internal pulldown resistor, a 470-Ω external pulldown is required. If the TRST pin is connected to multiple DSPs,

a buffer is recommended to ensure the VIL and VIH specifications are met.

Not Recommended For New Designs

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