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TMS320UC5409 bảng dữ liệu(PDF) 32 Page - Texas Instruments

tên linh kiện TMS320UC5409
Giải thích chi tiết về linh kiện  FIXED-POINT DIGITAL SIGNAL PROCESSOR
PDF  81 Pages
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TMS320UC5409 bảng dữ liệu(HTML) 32 Page - Texas Instruments

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TMS320UC5409
FIXEDPOINT DIGITAL SIGNAL PROCESSOR
SPRS101E − APRIL 1999 − REVISED OCTOBER 2008
32
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
DMA channel interrupt selection
The DMA controller can generate a CPU interrupt for each of the six channels. However, due to a limit on the
number of internal CPU interrupt inputs, channels 0, 1, 2, and 3 are multiplexed with other interrupt sources.
DMA channels 0, 1, 2, and 3 share an interrupt line with the receive and transmit portions of the McBSP. When
the UC5409 is reset, the interrupts from these three DMA channels are deselected. The INTSEL bit field in the
DMPREC register can be used to select these interrupts, as shown in Table 11.
Table 11. DMA Channel Interrupt Selection
INTSEL Value
IMR/IFR[6]
IMR/IFR[7]
IMR/IFR[10]
IMR/IFR[11]
00b (reset)
BRINT2
BXINT2
BRINT1
BXINT1
01b
BRINT2
BXINT2
DMAC2
DMAC3
10b
DMAC0
DMAC1
DMAC2
DMAC3
11b
Reserved
Not Recommended For New Designs



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