TMS28F008Axy,TMS28F800Axy

1048576 BY 8BIT/524288 BY 16BIT

AUTOSELECT BOOT BLOCK FLASH MEMORIES

SMJS851A − NOVEMBER 1997 − REVISED FEBRUARY 1998

37

POST OFFICE BOX 1443

power-up and reset switching characteristics for TMS28F008AZy and TMS28F800AZy over

recommended ranges of supply voltage (commercial and extended temperature ranges)

(see Notes 10, 11, and 12)

PARAMETER

ALT.

SYMBOL

’28F008AZy 70

’28F800AZy 70

’28F008AZy 80

’28F800AZy 80

UNIT

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

UNIT

tsu(VCC)

Setup time, RP low to VCC at 4.5 V MIN or 5.5 V MAX)

(see Note 13)

tPL5V

0

0

ns

ta(DV)

Address valid to data valid

tAVQV

70

80

ns

tsu(DV)

Setup time, RP high to data valid

tPHQV

450

450

ns

th(RP5)

Hold time, VCC at 4.5 V (MIN) to RP high

t5VPH

2

2

µs

NOTES: 10. Characterization data available

11. All ac current values are RMS unless otherwise noted.

12. E and G are switched low after power up.

13. The power supply can switch low concurrently with RP going low.

switching characteristics for TMS28F008AZy and TMS28F800AZy over recommended ranges of

supply voltage (commercial and extended temperature ranges)

read operations

PARAMETER

ALT.

SYMBOL

’28F008AZy 70

’28F800AZy 70

’28F008AZy 80

’28F800AZy 80

UNIT

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

UNIT

ta(A)

Access time, from A0 − A18 (see Note 14)

tAVQV

70

80

ns

ta(E)

Access time, from CE

tELQV

70

80

ns

ta(G)

Access time, from OE

tGLQV

35

40

ns

tc(R)

Cycle time, read

tAVAV

70

80

ns

td(E)

Delay time, CE low to low-impedance output

tELQX

0

0

ns

td(G)

Delay time, OE low to low-impedance output

tGLQX

0

0

ns

tdis(E)

Disable time, CE to high-impedance output

tEHQZ

25

30

ns

tdis(G)

Disable time, OE to high-impedance output

tGHQZ

25

30

ns

th(D)

Hold time, DQ valid from A0 − A17, CE, or OE, whichever occurs

first (see Note 14)

tAXQX

0

0

ns

tsu(EB)

Setup time, BYTE from CE low

tELFL

tELFH

5

5

ns

td(RP)

Delay time, output from RP high

tPHQV

450

450

ns

tdis(BL)

Disable time, BYTE low to DQ8 − DQ15 in the high-impedance

state

tFLQZ

70

80

ns

ta(BH)

Access time, from BYTE going high

tFHQV

70

80

ns

NOTE 14: For 28F800 (8-bit configuration) A−1, A−1 −A18 with A−1 as LSB address. For 28F008 (16-bit configuration): A0−A19 with A0 as LSB

address.