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UCD3138RMHR bảng dữ liệu(PDF) 19 Page - Texas Instruments |
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UCD3138RMHR bảng dữ liệu(HTML) 19 Page - Texas Instruments |
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19 / 78 page ![]() UCD3138 www.ti.com SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 3.5 PMBus/SMBus/I 2C Timing The timing characteristics and timing diagram for the communications interface that supports I2C, SMBus, and PMBus in Slave or Master mode are shown in Table 3-1, Figure 3-1, and Figure 3-2. The numbers in Table 3-1 arµe for 400 kHz operating frequency. However, the device supports all three speeds, standard (100 kHz), fast (400 kHz), and fast mode plus (1 MHz). Table 3-1. I2C/SMBus/PMBus Timing Characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Typical values at TA = 25°C and VCC = 3.3 V (unless otherwise noted) fSMB SMBus/PMBus operating frequency Slave mode, SMBC 50% duty cycle 100 1000 kHz fI2C I2C operating frequency Slave mode, SCL 50% duty cycle 100 1000 kHz Bus free time between start and t(BUF) 1.3 µs stop(1) t(HD:STA) Hold time after (repeated) start(1) 0.6 µs t(SU:STA) Repeated start setup time(1) 0.6 µs t(SU:STO) Stop setup time(1) 0.6 µs t(HD:DAT) Data hold time Receive mode 0 ns t(SU:DAT) Data setup time 100 ns t(TIMEOUT) Error signal/detect(2) 35 ms t(LOW) Clock low period 1.3 µs t(HIGH) Clock high period(3) 0.6 µs Cumulative clock low slave extend t(LOW:SEXT) 25 ms time(4) 20 + 0.1 tf Clock/data fall time Rise time tr = (VILmax – 0.15) to (VIHmin + 0.15) 300 ns Cb(5) 20 + 0.1 tr Clock/data rise time Fall time tf = 0.9 VDD to (VILmax – 0.15) 300 ns Cb(5) Cb Total capacitance of one bus line 400 pF (1) Fast Mode, 400 kHz (2) The device times out when any clock low exceeds t(TIMEOUT). (3) t(HIGH), Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction that is in progress. This specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0] = 0). (4) t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop. (5) Cb (pF) Figure 3-1. I2C/SMBus/PMBus Timing Diagram Copyright © 2012–2013, Texas Instruments Incorporated Electrical Specifications 19 Submit Documentation Feedback Product Folder Links: UCD3138 |
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