P89LPC932 datasheet(25/60 Pages) PHILIPS

25 / 60 page

Philips Semiconductors

P89LPC932

8-bit microcontroller with accelerated two-clock 80C51 core

Product data

Rev. 04 — 06 January 2004

25 of 60

9397 750 12379

the RTC during Power-down, there will be high power consumption. Please use an

external low frequency clock to achieve low power with the Real-Time Clock running

during Power-down.

8.15 Reset

The P1.5/RST pin can function as either an active-LOW reset input or as a digital

input, P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to ‘1’, enables the

external reset input function on P1.5. When cleared, P1.5 may be used as an input

pin.

Remark: During a power-up sequence, the RPE selection is overridden and this pin

will always function as a reset input. An external circuit connected to this pin

should not hold this pin LOW during a power-on sequence as this will keep the

device in reset. After power-up this input will function either as an external reset

input or as a digital input as deﬁned by the RPE bit. Only a power-up reset will

temporarily override the selection deﬁned by RPE bit. Other sources of reset will not

override the RPE bit.

Remark: During a power cycle, VDD must fall below VPOR (see Table 8 “DC electrical

characteristics” on page 45) before power is reapplied, in order to ensure a power-on

reset.

Reset can be triggered from the following sources:

• External reset pin (during power-up or if user conﬁgured via UCFG1);

• Power-on detect;

• Brownout detect;

• Watchdog Timer;

• Software reset;

• UART break character detect reset.

For every reset source, there is a ﬂag in the Reset Register, RSTSRC. The user can

read this register to determine the most recent reset source. These ﬂag bits can be

cleared in software by writing a ‘0’ to the corresponding bit. More than one ﬂag bit

may be set:

• During a power-on reset, both POF and BOF are set but the other ﬂag bits are

cleared.

• For any other reset, previously set ﬂag bits that have not been cleared will remain

set.

8.15.1

Reset vector

Following reset, the P89LPC932 will fetch instructions from either address 0000h or

the Boot address. The Boot address is formed by using the Boot Vector as the high

byte of the address and the low byte of the address = 00h.

The Boot address will be used if a UART break reset occurs, or the non-volatile Boot

Status bit (BOOTSTAT.0) = 1, or the device is forced into ISP mode during power-on

(see

P89LPC932 User’s Manual). Otherwise, instructions will be fetched from

address 0000H.

P89LPC932 bảng dữ liệu(PDF) 25 Page - NXP Semiconductors

P89LPC932 bảng dữ liệu(HTML) 25 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

bảng dữ liệu tải về

Link URL