LP3971 datasheet(22/52 Pages) TI1

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DATA OUTPUT

BY TRANSMITTER

DATA OUTPUT

BY RECEIVER

SCL FROM

MASTER

START

condition

acknowledge

C - bus.

clock pulse for

acknowledgement

VCC_APPS

9ROWDJH µµ$¶¶

9ROWDJH µµ%¶¶

5 Ps TYP

start

msb Chip Address lsb

SCL

msb Register Add lsb

msb

DATA

lsb

stop

SDA

start

Id = 34h

w ack

addr = 00h

ack

r ack

$GGUHVV K¶00 data

ack stop

msb Chip Address lsb

Id = 34h

ack

start

msb Chip Address lsb

ack

Msb Register Add lsb

ack

msb

DATA

lsb

ack

stop

SCL

SDA

start

Id = 34h

ack

addr = 02h

ack

DGGUHVV K¶02 data

stop

LP3971

SNVS432V – JANUARY 2006 – REVISED MAY 2013

www.ti.com

Write Cycle

Figure 20. Write cycle

Read Cycle

When a READ function is to be accomplished, a WRITE function must precede the READ function as follows.

Figure 21. Read Cycle

w = write (SDA = “0”)

r = read (SDA = “1”)

ack = acknowledge (SDA pulled down by either master or slave)

rs = repeated start

id = 34h (Chip Address)

Figure 22. I2C DVM Timing for VCC_APPS (Buck1)

LP3971 I

2C Register Definitions

I2C CONTROL REGISTERS

Read/

Address

Name

Write

8h'02

ISR

Interrupt Status Register A

8h'07

SCR1

R/W

System Control Register 1

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