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LP3913 bảng dữ liệu(PDF) 9 Page - Texas Instruments

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LP3913 bảng dữ liệu(HTML) 9 Page - Texas Instruments

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LP3913
www.ti.com
SNVS489I – NOVEMBER 2006 – REVISED SEPTEMBER 2013
OUTPUTS ELECTRICAL CHARACTERISTICS: CHG, STAT
Unless otherwise noted, VDD = 5V, VBATT = 3.6V. CBATT = 4.7 µF, CCHG_DET = 10 µF. Typical values and limits appearing in
normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for
operation, TJ = 0°C to +125°C.
(1) (2) (3) (4) (5)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
ILED
Output High Level
VLED = 2.0V
CHSPV Register (02)h bit 5
4
5
6
mA
= 1
ILED
Output High Level
VLED = 2.0V
CHSPV Register (02)h bit 5
8
10
12
mA
= 0
ILEAKAGE
Leakage Current
VLED = 1.5V, LED off
0.1
5
µA
LEDFREQ
Blinking Frequency
0.8
1
1.2
Hz
(1)
All voltages are with respect to the potential at the GND pin.
(2)
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power
dissipation exists, special care must be paid to thermal dissipation issues in board design.
(3)
Min and Max limits are specified by design, test, or statistical analysis. Typical numbers represent the most likely norm.
(4)
Low ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.
(5)
Typical values and limits appearing in normal type for TJ = 25°C. Limits appearing in boldfacetype apply over the entire junction
temperature range for operation,
−40°C to +125°C.
OUTPUTS ELECTRICAL CHARACTERISTICS: NRST, IRQB, ONSTAT
Unless otherwise noted, VDD = 5V, VBATT = 3.6V. CBATT = 4.7 µF, CCHG_DET = 10 µF. Typical values and limits appearing in
normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for
operation, TJ = 0°C to +125°C.
(1) (2) (3) (4) (5)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VOL
Output Low Level
IOL = 4 mA
0.4
V
ILEAKAGE
Leakage Current
VDD = 2.5V, Output Logic
−1
1
µA
High
(1)
All voltages are with respect to the potential at the GND pin.
(2)
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power
dissipation exists, special care must be paid to thermal dissipation issues in board design.
(3)
Min and Max limits are specified by design, test, or statistical analysis. Typical numbers represent the most likely norm.
(4)
Low ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.
(5)
Typical values and limits appearing in normal type for TJ = 25°C. Limits appearing in boldfacetype apply over the entire junction
temperature range for operation,
−40°C to +125°C.
INPUTS ELECTRICAL CHARACTERISTICS: USBSUSP, USBISEL
Unless otherwise noted, VUSB = 5V, VBATT = 3.6V. CBATT = 4.7 µF, CCHG_DET = 10 µF. Typical values and limits appearing in
normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for
operation, TJ = 0°C to +125°C.
(1) (2) (3) (4) (5) (6)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VIL
Input Low Level
0.3*VUSB
V
VIH
Input High Level
0.7*VUSB
V
ILEAKAGE
Input Leakage
−1
1
µA
(1)
All voltages are with respect to the potential at the GND pin.
(2)
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power
dissipation exists, special care must be paid to thermal dissipation issues in board design.
(3)
Min and Max limits are specified by design, test, or statistical analysis. Typical numbers represent the most likely norm.
(4)
Low ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.
(5)
Typical values and limits appearing in normal type for TJ = 25°C. Limits appearing in boldfacetype apply over the entire junction
temperature range for operation,
−40°C to +125°C.
(6)
LDO2EN, BUCK1EN, and USBSUSP have weak internal pull downs while pins POWERACK, ONOFF do not have this.
Copyright © 2006–2013, Texas Instruments Incorporated
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