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2015-07-0038

PT0535-4

8/18/15

6

PI4MSD5V9543B

2 Channel I2C bus switch

with Interrupt Logic and Reset

Application

Figure 3. Typical Application

VCC

VPU1

VPU2

1.8V

1.5V-5.5V

1.2V-5.5V

2.5V

1.8V-5.5V

1.8V-5.5V

3.3V

2.7V-5.5V

2.7V-5.5V

5V

4.5V-5.5V

4.5V-5.5V

Note:

If the device generating the interrupt has an open-drain output structure or can be 3-stated, a pull-up resistor is required.

If the device generating the interrupt has a totem pole output structure and cannot be 3-stated, a pull-up resistor is not required.

The interrupt inputs should not be left floating.

Device addressing

Following a START condition the bus master must output the address of the slave it is accessing. The address of

the PI4MSD5V9543B is shown in Figure 4.

To conserve power, no internal pull-up resistors are incorporated on the hardware selectable address pins and they

must be pulled HIGH or LOW.

The last bit of the slave address defines the operation to be performed. When set to logic 1 a read is selected, while

a logic 0 selects a write operation.

I2C bus master