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SN74LVC112ADBLE bảng dữ liệu(PDF) 5 Page - Texas Instruments

tên linh kiện SN74LVC112ADBLE
Giải thích chi tiết về linh kiện  SN74LVC112A Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset
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SN74LVC112ADBLE bảng dữ liệu(HTML) 5 Page - Texas Instruments

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SN74LVC112A
www.ti.com
SCAS289M – JANUARY 1993 – REVISED DECEMBER 2014
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
Operating
1.65
3.6
VCC
Supply voltage
V
Data retention only
1.5
VCC = 1.65 V to 1.95 V
0.65 × VCC
VIH
High-level input voltage
VCC = 2.3 V to 2.7 V
1.7
V
VCC = 2.7 V to 3.6 V
2
VCC = 1.65 V to 1.95 V
0.35 × VCC
VIL
Low-level input voltage
VCC = 2.3 V to 2.7 V
0.7
V
VCC = 2.7 V to 3.6 V
0.8
VI
Input voltage
0
5.5
V
VO
Output voltage
0
VCC
V
VCC = 1.65 V
–4
VCC = 2.3 V
–8
IOH
High-level output current
mA
VCC = 2.7 V
–12
VCC = 3 V
–24
VCC = 1.65 V
4
VCC = 2.3 V
8
IOL
Low-level output current
mA
VCC = 2.7 V
12
VCC = 3 V
24
Δt/Δv
Input transition rise or fall rate
10
ns/V
TA
Operating free-air temperature
–40
125
°C
(1)
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004).
7.4 Thermal Information
SN74LVC112A
THERMAL METRIC(1)
D
DB
DGV
NS
PW
UNIT
24 PINS
RθJA
Junction-to-ambient thermal resistance
90.6
107.1
129.0
90.7
122.6
RθJC(to
Junction-to-case (top) thermal resistance
50.9
59.6
52.1
48.3
51.4
p)
°C/W
RθJB
Junction-to-board thermal resistance
44.8
54.4
62.0
49.4
64.4
ψJT
Junction-to-top characterization parameter
14.7
20.5
6.5
14.6
6.7
ψJB
Junction-to-board characterization parameter
44.5
53.8
61.3
49.1
63.8
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 1993–2014, Texas Instruments Incorporated
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Product Folder Links: SN74LVC112A



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