TUSB5052PZ datasheet(58/82 Pages) TI

58 / 82 page

7−10

7.2.1

Receiver Data Flow

Every UART receiver has a 32-byte FIFO. The receiver FIFO has two trigger levels. One is the high-level mark

(HALT), which is set to 12 bytes, and the other is the low-level mark (RESTORE), which is set to 4-bytes. When the

HALT mark is reached, either the RTS pin goes high or Xoff is transmitted (depending on the auto setting). When the

FIFO reaches the RESTORE mark, then either the RTS pin goes low or Xon is transmitted.

64-Byte

Y-Buffer

64-Byte

X-Buffer

DMA

DMACDR

UBM

X/Y

Receiver

Halt on Error or Time-Out

RDR: 32-Byte FIFO

RTS/DTR = 1

or Xoff Transmitted

RTS/DTR = 0

or Xon Transmitted

Xoff/Xon

CTS/DTR = 1/0

64-Byte

Y-Buffer

64-Byte

X-Buffer

DMA

DMACDR

SIN

SOUT

TDR

Pause/Run

Host

Figure 7−2. Receiver/Transmitter Data Flow

7.2.2

Hardware Flow Control

Figure 7−3 illustrates the connection necessary to achieve hardware flow control. CTS and RTS signals are provided

for this purpose. Auto-CTS and auto-RTS (and Xon/Xoff) can be enabled/disabled independently by programming

the FCRL register.

TUSB5052

SIN

RTS

SOUT

CTS

External Device

SOUT

CTS

SIN

RTS

Figure 7−3. Auto Flow Control Interconnect

7.2.3

Auto-RTS (Receiver Control)

In this mode, the RTS output pin signals the receiver FIFO status to an external device. The RTS output signal is

controlled by the high-level and low-level marks of the FIFO. When the high-level mark is reached, RTS goes high,

signaling to an external sending device to halt its transfer. Conversely, when the low-level mark is reached, RTS goes

low, signaling to an external sending device to resume its transfer. Data transfer from the FIFO to the X/Y-buffer is

performed by the DMA controller. See section 6.2 for DMA transfer termination conditions.

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