TMS320DM640 datasheet(100/171 Pages) TI

100 / 171 page

Clock PLL

100

June 2003 − Revised August 2004

SPRS222C

PLLMULT

PLLCLK

CLKMODE0

CLKMODE1

CLKIN

EMI

filter

3.3 V

00 01 10

CPU Clock

Peripheral Bus, EDMA

Clock

Timer Internal Clock

CLKOUT4, Peripheral Clock

(AUXCLK for McASP),

McBSP Internal Clock

CLKOUT6

EMIF

00 01 10

EK2RATE

(GBLCTL.[19,18])

ECLKOUT2

ECLKOUT1

PLL

x6, x12

µF 0.1 µF

AEA[20:19]

(For the PLL Options, CLKMODE Pins Setup, and

PLL Clock Frequency Ranges, see Table 9.)

Internal to DM641/DM640

PLLV

ECLKIN

NOTES: A. Place all PLL external components (C1, C2, and the EMI Filter) as close to the C6000

 DSP device as possible. For the best

performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or

components other than the ones shown.

B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (C1, C2, and the EMI

Filter).

C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.

D. EMI filter manufacturer TDK part number ACF451832-333, -223, -153, -103. Panasonic part number EXCCET103U.

Figure 4−10. External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode

TMS320DM640 bảng dữ liệu(PDF) 100 Page - Texas Instruments

TMS320DM640 bảng dữ liệu(HTML) 100 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL