AC Electrical Characteristics

T

LVDS Data Input

Symbol

Parameter

Conditions

Min

Max

Units

RPLLS

FPD-Link Receiver Phase Lock Loop Wake-up Time

10

ms

RSKM

RxIN Skew Margin (Note 2) and (Figure 7)V

CLK = 85 MHz

240

ps

Note 2: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account transmitter pulse positions (min

and max) and the receiver input setup and hold time (internal data sampling window: RSPOS). This margin allows for LVDS interconnect skew, inter-symbol

interference (both dependent on type and length of cable), and source clock (FPD-Link Transmitter TxCLK IN) jitter. The specified RSKM minimum assumes a

TPPOS max of 200 ps.

RSKM = cable skew (type, length) + source clock jitter (cycle to cycle) + remaining margin for data sampling (

≥0)

This parameter is guaranteed by design. The limits are based on statistical analysis of the device performance over PVT (Process, Voltage, Temperature) range.

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Acronyms:

RSKM

Receiver Skew Margin

TPPOS

Transmitter Pulse Position

RSPOS

Receiver Strobe Position

SW

Strobe Width

Definitions:

SW:

Setup and Hold Time (Internal data sampling window)

RSKM:

Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) + Remaining margin for data sampling (

≥ 0)

Cable Skew: Typically 10 ps − 40 ps per foot.

FIGURE 7. FPD-Link Receiver Input Skew Margin

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FIGURE 8. Ideal Strobe Position for LVDS Input

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