SN65LVDS93A-Q1

SLLSEM1B – FEBRUARY 2015 – REVISED APRIL 2015

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6.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Delay time, CLKOUT

↑ after Yn valid

(serial bit position 0, equal D1, D9,

-0.1

0

0.1

ns

D20, D5)

Delay time, CLKOUT

↑ after Yn valid

(serial bit position 1, equal D0, D8,

ns

D19, D27)

Delay time, CLKOUT

↑ after Yn valid

(serial bit position 2, equal D7, D18,

ns

D26. D23)

Delay time, CLKOUT

↑ after Yn valid

(serial bit position 3; equal D6, D15,

ns

D25, D17)

Delay time, CLKOUT

↑ after Yn valid

(serial bit position 4, equal D4, D14,

ns

D24, D16)

Delay time, CLKOUT

↑ after Yn valid

(serial bit position 5, equal D3, D13,

ns

D22, D11)

Delay time, CLKOUT

↑ after Yn valid

(serial bit position 6, equal D2, D12,

ns

D21, D10)

Output clock period

ns

±26

Figure 11

±44

modulated at 3MHz, see Figure 11

ps

±35

see Figure 11

±42

modulated at 3MHz, see Figure 11

High-level output clock pulse

ns

duration

Differential output voltage transition

See Figure 7

225

500

ps

Enable time, SHTDN

↑ to phase lock

6

µs

(Yn valid)

Disable time, SHTDN

↓ to off-state

7

ns

(CLKOUT high-impedance)

(1)

(2)

|Input clock jitter| is the magnitude of the change in the input clock period.

(3)

The output clock cycle-to-cycle jitter is the largest recorded change in the output clock period from one cycle to the next cycle observed

over 15,000 cycles.Tektronix TDSJIT3 Jitter Analysis software was used to derive the maximum and minimum jitter value.

8

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