TAS5112DFD datasheet(11/19 Pages) TI

11 / 19 page

TAS5112

SLES048C − JULY 2003 − REVISED MARCH 2004

www.ti.com

THEORY OF OPERATION

POWER SUPPLIES

The power device only requires two supply voltages,

GVDD and PVDD_X.

GVDD is the gate drive supply for the device, regulated

internally down to approximately 12 V, and decoupled with

regards to board GND on the GREG pins through an

external capacitor. GREG powers both the low side and

high side via a bootstrap step-up conversion. The

bootstrap supply is charged after the first low-side turn-on

pulse. Internal digital core voltage DREG is also derived

from GVDD and regulated down by internal circuitry to

3.3 V.

The gate-driver regulator can be bypassed for reducing

idle loss in the device by shorting GREG to GVDD and

directly feeding in 12.0 V. This can be useful in an

application where thermal conduction of heat from the

device is difficult.

PVDD_X is the H-bridge power supply pin. Two power pins

exists for each half-bridge to handle the current density. It

is important that the circuitry recommendations around

the PVDD_X pins are followed carefully both topology-

and layout-wise. For topology recommendations, see the

Typical System Configuration section. Following these

recommendations is important for parameters like EMI,

reliability, and performance.

POWERING UP

RESET

GVDD

PVDD_x

PWM_xP

> 1 ms

NOTE: PVDD should not be powered up before GVDD.

During power up when RESET is asserted LOW, all

MOSFETs are turned off and the two internal half-bridges

are in the high-impedance state (Hi-Z). The bootstrap

capacitors supplying high-side gate drive are not charged

at this point. To comply with the click and pop scheme and

use of non-TI modulators it is recommended to use a 4-k

Ω

pulldown resistor on each PWM output node to ground.

This precharges the bootstrap supply capacitors and

discharges the output filter capacitor (see the Typical

TAS5112 Application Configuration section).

After GVDD has been applied, it takes approximately 800

µs to fully charge the BST capacitor. Within this time,

RESET must be kept low. After approximately 1 ms, the

back-end bootstrap capacitor is charged.

RESET can now be released if the modulator is powered

up and streaming valid PWM signals to the back-end

PWM_xP. Valid means a switching PWM signal which

complies with the frequency and duty cycle ranges stated

in the Recommended Operating Conditions.

A constant HIGH dc level on the PWM_xP is not permitted,

because it would force the high-side MOSFET ON until it

eventually ran out of BST capacitor energy and might

damage the device.

An unknown state of the PWM output signals from the

modulator is illegal and should be avoided, which in

practice means that the PWM processor must be powered

up and initialized before RESET is de-asserted HIGH to

the back end.

POWERING DOWN

For power down of the back end, an opposite approach is

necessary. The RESET must be asserted LOW before the

valid PWM signal is removed.

When PWM processors are used with TI PurePath Digital

amplifiers, the correct timing control of RESET and

PWM_xP is performed by the modulator.

PRECAUTION

The TAS5112 must always start up in the high-impedance

(Hi-Z) state. In this state, the bootstrap (BST) capacitor is

precharged by a resistor on each PWM output node to

ground. See the system configuration. This ensures that

the back end is ready for receiving PWM pulses, indicating

either HIGH- or LOW-side turnon after RESET is

de-asserted to the back end.

With the following pulldown resistor and BST capacitor

size, the charge time is:

C = 33 nF, R = 4.7 k

Ω

× C × 5 = 775.5 µs

After GVDD has been applied, it takes approximately 800

µs to fully charge the BST capacitor. During this time,

RESET must be kept low. After approximately 1 ms the

back end BST is charged and ready. RESET can now be

released if the PWM modulator is ready and is streaming

valid PWM signals to the back end. Valid PWM signals are

switching PWM signals with a frequency between

350−400 kHz. A constant HIGH level on the PWM+ would

force the high-side MOSFET ON until it eventually ran out

of BST capacitor energy. Putting the device in this

condition should be avoided.

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