TAS5112

SLES048C − JULY 2003 − REVISED MARCH 2004

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6

ELECTRICAL CHARACTERISTICS

PVDD_x = 29.5 V, GVDD = 29.5 V, DVDD connected to DREG via a 100-

Ω resistor, RL = 6 Ω, 8X fs = 384 kHz, unless otherwise noted

TYPICAL

OVER TEMPERATURE

SYMBOL

PARAMETER

TEST CONDITIONS

TA=25°C

TA=25°C

TCase=

75

°C

TA=40°C

TO 85

°C

UNITS

MIN/TYP/

MAX

INPUT/OUTPUT PROTECTION

Vuvp,G

Undervoltage protection

Set the DUT in normal

operation mode with all the

protections enabled. Sweep

GVDD up and down. Monitor

7.4

6.9

V

Min

Vuvp,G

Undervoltage protection

limit, GVDD

GVDD up and down. Monitor

SD output. Record the

GREG reading when SD is

triggered.

7.4

7.9

V

Max

OTW

Overtemperature warning,

junction temperature

125

°C

Typ

OTE

Overtemperature error,

junction temperature

150

°C

Typ

OC

Overcurrent protection

See Note 1.

5.8

A

Typ

STATIC DIGITAL SPECIFICATION

PWM_AP, PWM_BP, M1,

M2, M3, SD, OTW

VIH

High-level input voltage

2

V

Min

VIH

High-level input voltage

DVDD

V

Max

VIL

Low-level input voltage

0.8

V

Max

Leakage

Input leakage current

−10

µA

Min

Leakage

Input leakage current

10

µA

Max

OTW/SHUTDOWN (SD)

Internally pull up R from

OTW/SD to DVDD

30

22.5

k

Ω

Min

VOL

Low-level output voltage

IO = 4 mA

0.4

V

Max

(1) To optimize device performance and prevent overcurrent (OC) protection tripping, the demodulation filter must be designed with special care. See

Demodulation Filter Design in the Application Information section of the data sheet and consider the recommended inductors and capacitors for

optimal performance. It is also important to consider PCB design and layout for optimum performance of the TAS5112. It is recommended to follow

the TAS5112F2EVM (S/N 112) design and layout guidelines for best performance.