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WM8993 bảng dữ liệu(PDF) 158 Page - Wolfson Microelectronics plc

tên linh kiện WM8993
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WM8993 bảng dữ liệu(HTML) 158 Page - Wolfson Microelectronics plc

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WM8993
Production Data
w
PD, November 2010, Rev 4.0
158
POWER ON RESET
The WM8993 includes Power-On Reset (POR) circuits, which are used to reset the digital logic into a
default state after power up. The POR circuits derive their output from AVDD1, AVDD2 and DCVDD.
The internal POR
¯¯¯ signal is asserted low when AVDD1, AVDD2 and DCVDD are all below minimum
thresholds.
The specific behaviour of the circuit will vary, depending on relative timing of the supply voltages.
Typical scenarios are illustrated in Figure 69 and Figure 70.
Figure 69 Power On Reset timing – AVDD1/2 enabled first
Figure 70 Power On Reset timing - DCVDD enabled first
The POR
¯¯¯ signal is undefined until AVDD1 or AVDD2 has exceeded the minimum threshold, Vpora_on
Once this threshold has been exceeded, POR
¯¯¯ is asserted low and the chip is held in reset. In this
condition, all writes to the control interface are ignored. Once AVDD1, AVDD2 and DCVDD have all



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