WM8993 datasheet(137/229 Pages) WOLFSON

137 / 229 page

Production Data

WM8993

PD, November 2010, Rev 4.0

137

CONTROL INTERFACE

The WM8993 is controlled by writing to registers through a 2-wire serial control interface. Readback

is available for all registers, including device ID, power management status and GPIO status.

The WM8993 is a slave device on the control interface; SCLK is a clock input, while SDAT is a bi-

directional data pin. To allow arbitration of multiple slaves (and/or multiple masters) on the same

interface, the WM8993 transmits logic 1 by tri-stating the SDAT pin, rather than pulling it high. An

external pull-up resistor is required to pull the SDAT line high so that the logic 1 can be recognised

by the master.

In order to allow many devices to share a single 2-wire control bus, every device on the bus has a

unique 7-bit device ID (this is not the same as the 8-bit address of each register in the WM8993).

The WM8993 device ID is 0011 0100 (34h). The LSB of the device ID is the Read/Write bit; this bit is

set to logic 1 for “Read” and logic 0 for “Write”.

The WM8993 operates as a slave device only. The controller indicates the start of data transfer with

a high to low transition on SDAT while SCLK remains high. This indicates that a device ID, register

address and data will follow. The WM8993 responds to the start condition and shifts in the next eight

bits on SDAT (7-bit device ID + Read/Write bit, MSB first). If the device ID received matches the

device ID of the WM8993, then the WM8993 responds by pulling SDAT low on the next clock pulse

(ACK). If the device ID is not recognised or the R/W bit is set incorrectly, the WM8993 returns to the

idle condition and waits for a new start condition and valid address.

If the device ID matches the device ID of the WM8993, the data transfer continues as described

below. The controller indicates the end of data transfer with a low to high transition on SDAT while

SCKL remains high. After receiving a complete address and data sequence the WM8993 returns to

the idle state and waits for another start condition. If a start or stop condition is detected out of

sequence at any point during data transfer (i.e. SDAT changes while SCLK is high), the device

returns to the idle condition.

The WM8993 supports the following read and write operations:



Single write



Single read



Multiple write using auto-increment



Multiple read using auto-increment

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