DP83932C datasheet(84/98 Pages) NSC

84 / 98 page

70 AC and DC Specifications (Continued)

BUS REQUEST TIMING BMODE e 0

TLF10492 – 67

Number

Parameter

20 MHz

25 MHz

33 MHz

Units

Min

Max

Min

Max

Min

Max

T43

BSCK to HOLD High (Note 2)

T44

BSCK to HOLD Low (Note 2)

T45

HLDA Synchronous Setup Time to BSCK (Note 5)

T46

HLDA Synchronous Deassert Setup Time (Note 1)

T51

BSCK to Address ADS MWR DS ECS

USRk10l and EXUSRk30lTRI-STATE

(Note 4)

T52

BSCK to Data TRI-STATE

T53

BSCK to USRk10l or EXUSRk30lValid

T55

BSCK to Bus Status Valid

T55b

Sk20l Hold from BSCK

Note 1

A block transfer by the SONIC can be pre-empted from the bus by deasserting HLDA provided HLDA is deasserted T46 before the rising edge of the last

T2 in the current access

Note 2

The assertion edge for HOLD is dependent upon the PH bit in the DCR2 The default situation is shown wih a solid line in the timing diagram T43 and T44

apply for both modes Also if HLDA is asserted when the SONIC wants to acquire the bus HOLD will not be asserted until HLDA has been deasserted first

Note 3

Sk20l will indicate IDLE at the end of T2 if the last operation is a read operation or at the end of Th if the last operation is a write operation

Note 4

This timing value includes an RC delay inherent in the test measurement These signals typically TRI-STATE 7 ns earlier enabling other devices to drive

these lines without contention

Note 5

The HLDA signal is sampled by the SONIC on each rising edge of BSCK The maximum setup time is ((BSCK

period–T45

min

spec)–5ns) The HLDA

max setup time is for information only and is not tested

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