AN983 datasheet(53/91 Pages) ETC

53 / 91 page

AN983B

PCI/miPCI Fast Ethernet Controller with integrated PHY

First descriptor.

Last descriptor.

Too long packet (packet length > 1518 bytes). This bit is valid only in last descriptor

Late collision. Set when collision is active after 64 bytes. This bit is valid only in last

descriptor

Frame type. This bit is valid only in last descriptor.

1: Ethernet type

0: 802.3 type

Receive watchdog (refer to CSR15, bit 4). This bit is valid only in last descriptor.

Reserved Default = 0

Dribble bit. This bit is valid only in last descriptorEC

Packet length is not integer multiple of 8-bit.

CRC error. This bit is valid only in last descriptor

Overflow. This bit is valid only in last descriptor

RDES1

Bit #

Name

Descriptions

31~26

---

Reserved

RER

Receive end of ring

Indicates this descriptor is last, return to base address of descriptor

RCH

Second address chain

Use for chain structure. Indicates the buffer2 address is the next descriptor address.

Ring mode takes precedence over chained mode

23~22

---

Reserved

21~11

RBS2

Buffer 2 size (DW boundary)

10~ 0

RBS1

Buffer 1 size (DW boundary)

RDES2

Bit #

Name

Descriptions

31~0

RBA1

Receive Buffer Address 1. This buffer address should be double word aligned.

RDES3

Bit #

Name

Descriptions

31~0

RBA2

Receive Buffer Address 2. This buffer address should be double word aligned.

7.4.2. TRANSMIT DESCRIPTOR

7.4.2.1. Transmit Descriptor Table

ADMtek Inc.

www.admtek.com.tw

Rev. 1.8

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