ADUC848BCP8-5 datasheet(42/108 Pages) AD

42 / 108 page

ADuC845/ADuC847/ADuC848

Rev. A | Page 42 of 108

Notes on the ADCMODE Register

•

Any change to the MD bits immediately resets both ADCs

(auxiliary ADC only applicable to the ADuC845). A write

to the MD2–MD0 bits with no change in contents is also

treated as a reset. (See the exception to this in the third

note of this section.)

•

If ADC0CON is written when ADC0EN = 1, or if

ADC0EN is changed from 0 to 1, both ADCs are also

immediately reset. In other words, the primary ADC is

given priority over the auxiliary ADC and any change

requested on the primary ADC is immediately responded

to. Only applicable to the ADuC845.

•

On the other hand, if ADC1CON is written to or if

ADC1EN is changed from 0 to 1, only the auxiliary ADC is

reset. For example, if the primary ADC is continuously

converting when the auxiliary ADC change or enable

occurs, the primary ADC continues undisturbed. Rather

than allow the auxiliary ADC to operate with a phase

difference from the primary ADC, the auxiliary ADC falls

into step with the outputs of the primary ADC. The result

is that the first conversion time for the auxiliary ADC is

delayed by up to three outputs while the auxiliary ADC

update rate is synchronized to the primary ADC. Only

applicable to ADuC845. If the ADC1CON write occurs

after the primary ADC has completed its operation, the

auxiliary ADC can respond immediately without having to

fall into step with the primary ADCs output cycle.

•

If the parts are powered down via the PD bit in the PCON

they are not reset to default state. Upon a subsequent

resumption of normal operating mode, the ADCs restarts

the selected operation defined by the ADCMODE register.

•

Once ADCMODE has been written with a calibration

mode, the RDY0/1 (ADuC845 only) bits (ADCSTAT) are

reset and the calibration commences. On completion, the

appropriate calibration registers are written, the relevant

bits in ADCSTAT are written, and the MD2–MD0 bits are

reset to 000b to indicate that the ADC is back in power-

down mode.

•

Any calibration request of the auxiliary ADC while the

temperature sensor is selected fails to complete. Although

the RDY1 bit is set at the end of the calibration cycle, no

update of the calibration SFRs takes place, and the ERR1

bit is set. ADuC845 only.

•

Calibrations performed at maximum SF (see Table 28)

value (slowest ADC throughput rate) help to ensure

optimum calibration.

•

The duration of a calibration cycle is 2/Fadc for chop-on

mode and 4/Fadc for chop-off mode.

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