DSD1791 datasheet(49/56 Pages) TI1

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DSD1791

SLES072B − MARCH 2003 − REVISED NOVEMBER 2006

www.ti.com

THEORY OF OPERATION

Analog

Voltage

Output

Digital

Input

24 Bit

8 fS

MSB and

Lower 18 Bit

Upper 6 Bit

ICOB

Decoder

3rd-Order

5-Level

Sigma-Delta

Advanced

DWA

Current

Segment

DAC

0–4

Level

0–62

Level

0–66

I/V

Converter

Figure 60. Advanced Segment DAC With I/V Converter

The DSD1791 uses TI’s advanced segment DAC architecture to achieve excellent dynamic performance and

improved tolerance to clock jitter. The DSD1791 provides balanced voltage outputs.

Digital input data via the digital filter is separated into 6 upper bits and 18 lower bits. The 6 upper bits are converted

to inverted complementary offset binary (ICOB) code. The lower 18 bits, in association with the MSB, are processed

by a five-level third-order delta-sigma modulator operated at 64 fS by default. The 1 level of the modulator is equivalent

to the 1 LSB of the ICOB code converter. The data groups processed in the ICOB converter and third-order

delta-sigma modulator are summed together to an up to 66-level digital code, and then processed by data-weighted

averaging (DWA) to reduce the noise produced by element mismatch. The data of up to 66 levels from the DWA is

converted to an analog output in the differential-current segment section.

This architecture has overcome the various drawbacks of conventional multibit processing and also achieves

excellent dynamic performance.

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