DSD1791 datasheet(36/56 Pages) TI1

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DSD1791

SLES072B − MARCH 2003 − REVISED NOVEMBER 2006

www.ti.com

Pin Assignment When Using the DSD Format Interface

D DSDL (pin 25): L-channel DSD data input

D DSDR (pin 24): R-channel DSD data input

D DBCK (pin 4): Bit clock (BCK) for DSD data

Requirements for System Clock

The bit clock (DBCK) for the DSD mode is required at pin 4 of the DSD1791. The frequency of the bit clock may be

N times the sampling frequency. Generally, N is 64 in DSD applications.

The interface timing between the bit clock and DSDL and DSDR is required to meet the setup and hold time

specifications shown in Figure 40.

The SCK is not necessary after the mode change to the DSD mode is done.

t = 1/(64

× 44.1 kHz)

DSDL

DSDR

DBCK

Figure 39. Normal Data Output Form From DSD Decoder

DSDL

DSDR

t(BCH)

DBCK

t(BCL)

t(BCY)

1.4 V

t(DS)

t(DH)

PARAMETER

MIN

MAX

UNITS

t(BCY) DBCK pulse cycle time

85(1)

t(BCH) DBCK high-level time

t(BCL) DBCK low-level time

t(DS)

DSDL, DSDR setup time

t(DH)

DSDL, DSDR hold time

(1) 2.8224 MHz × 4. (2.8224 MHz = 64 × 44.1 kHz. This value is specified as a

sampling rate of DSD.)

Figure 40. Timing for DSD Audio Interface

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