DEN

VODSEL

TRFB

24

REN

RRFB

RPWDNB

TCLK

TPWDNB

SERIALIZER ± DS99R101

PLL

Timing

and

Control

RIN-

DESERIALIZER ± DS99R102

PLL

Timing

and

Control

24

LOCK

RCLK

Clock

Recovery

DS99R101, DS99R102

SNLS240D – MARCH 2007 – REVISED APRIL 2013

www.ti.com

Block Diagram

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings

(1) (2)

−0.3V to +4V

LVCMOS/LVTTL Input Voltage

LVCMOS/LVTTL Output Voltage

LVDS Receiver Input Voltage

−0.3V to 3.9V

LVDS Driver Output Voltage

−0.3V to 3.9V

LVDS Output Short Circuit Duration

10 ms

Junction Temperature

+150°C

Storage Temperature

−65°C to +150°C

Lead Temperature (Soldering, 4 seconds)

+260°C

Maximum Package Power Dissipation Capacity

48L TQFP

Package

De-rating:

1/

DS99R101

21.0°C/W

DS99R102

21.1°C/W

ESD Rating (HBM)

≥±8 kV

(1)

“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of

device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or

other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating

Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.

(2)

If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.

(3)

JEDEC

2

Submit Documentation Feedback

Copyright © 2007–2013, Texas Instruments Incorporated

Product Folder Links: DS99R101 DS99R102