DS90C124IVSSLASHNOPB datasheet(7/31 Pages) TI1

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TCLK

ODD DIN

EVEN DIN

Signal Pattern

Device Pin Name

DS90C124, DS90C241

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SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013

Deserializer Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol

Parameter

Conditions

Pin/Freq.

Min

Typ

Max

Units

tRCP

Receiver out Clock Period

tRCP = tTCP

(1)

RCLK

28.6

200

tRDC

RCLK Duty Cycle

RCLK

tCLH

LVCMOS Low-to-High

CL = 8 pF

ROUT [23:0],

2.5

3.5

Transition Time

(lumped load)

LOCK, RCLK

(Figure 11)(1)

tCHL

LVCMOS High-to-Low

2.5

3.5

Transition Time

tROS

ROUT (7:0) Setup Data to RCLK

(Figure 15)

ROUT [7:0]

(0.40)*

(29/56)*tR

(Group 1)

tRCP

tROH

ROUT (7:0) Hold Data to RCLK

(0.40)*

(27/56)*tR

(Group 1)

tRCP

tROS

ROUT (15:8) Setup Data to RCLK

(Figure 15)

ROUT [15:8],

(0.40)*

0.5*tRCP

(Group 2)

LOCK

tRCP

tROH

ROUT (15:8) Hold Data to RCLK

(0.40)*

0.5*tRCP

(Group 2)

tRCP

tROS

ROUT (23:16) Setup Data to

(Figure 15)

ROUT [23:16]

(0.40)*

(27/56)*tR

RCLK (Group 3)

tRCP

tROH

ROUT (23:16) Hold Data to RCLK

(0.40)*

(29/56)*tR

(Group 3)

tRCP

tHZR

HIGH to TRI-STATE Delay

(Figure 13)

ROUT [23:0],

RCLK, LOCK

tLZR

LOW to TRI-STATE Delay

tZHR

TRI-STATE to HIGH Delay

tZLR

TRI-STATE to LOW Delay

tDD

Deserializer Delay

(Figure 12)

RCLK

[4+(3/56)]

T +5.9

T +14

tDRDL

Deserializer PLL Lock Time from

(Figure 14) (2) (1)

5 MHz

Powerdown

35 MHz

RxIN_TOL Receiver INput TOLerance Left,

(Figure 16)(3) (1) (4)

5 MHz–35 MHz

0.25

RxIN_TOL Receiver INput TOLerance Right,

(Figure 16)(3) (1) (4)

5 MHz–35 MHz

0.25

(1)

Specification is ensured by characterization and is not tested in production.

(2)

The Deserializer PLL lock time (tDRDL) may vary depending on input data patterns and the number of transitions within the pattern.

(3)

RxIN_TOL is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors

occur. It is a measurement in reference with the ideal bit position, please see AN-1217 (SNLA053) for detail.

(4)

UI – Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency.

AC TIMING DIAGRAMS AND TEST CIRCUITS

Figure 1. Serializer Input Checkerboard Pattern

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